Fast instruction cache analysis via static cache simulation

Proceedings of Simulation Symposium ◽

10.1109/simsym.1995.393589 ◽

2002 ◽

Author(s):

F. Mueller ◽

D.B. Whalley

Keyword(s):

Instruction Cache ◽

Cache Simulation ◽

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A Vulnerability in RSA Implementations Due to Instruction Cache Analysis and Its Demonstration on OpenSSL

Topics in Cryptology – CT-RSA 2008 - Lecture Notes in Computer Science ◽

10.1007/978-3-540-79263-5_16 ◽

2008 ◽

pp. 256-273 ◽

Author(s):

Onur Acıiçmez ◽

Werner Schindler

Keyword(s):

Instruction Cache ◽

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Fast instruction cache simulation strategies in a hardware/software co-design environment

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) ◽

10.1109/aspdac.1999.760030 ◽

1999 ◽

Author(s):

M. Lajolo ◽

L. Lavagno ◽

A. Sangiovanni-Vincentelli

Keyword(s):

Design Environment ◽

Instruction Cache ◽

Cache Simulation

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Learning Bayesian Networks for Improved Instruction Cache Analysis

2010 Ninth International Conference on Machine Learning and Applications ◽

10.1109/icmla.2010.68 ◽

2010 ◽

Author(s):

Mark Bartlett ◽

Iain Bate ◽

James Cussens

Keyword(s):

Bayesian Networks ◽

Instruction Cache ◽

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Compositional static instruction cache simulation

Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '04 ◽

10.1145/997163.997183 ◽

2004 ◽

Author(s):

Kaustubh Patil ◽

Kiran Seth ◽

Frank Mueller

Keyword(s):

Instruction Cache ◽

Cache Simulation

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Probabilistic Instruction Cache Analysis Using Bayesian Networks

2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications ◽

10.1109/rtcsa.2011.55 ◽

2011 ◽

Author(s):

Mark Bartlett ◽

Iain Bate ◽

James Cussens ◽

Dimitar Kazakov

Keyword(s):

Bayesian Networks ◽

Instruction Cache ◽

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Instruction Trace Compression for Rapid Instruction Cache Simulation

2007 Design, Automation & Test in Europe Conference & Exhibition ◽

10.1109/date.2007.364389 ◽

2007 ◽

Author(s):

Andhi Janapsatya ◽

Aleksandar Ignjatovic ◽

Sri Parameswaran ◽

Joerg Henkel

Keyword(s):

Instruction Cache ◽

Cache Simulation ◽

Trace Compression

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Compositional static instruction cache simulation

ACM SIGPLAN Notices ◽

10.1145/998300.997183 ◽

2004 ◽

Vol 39 (7) ◽

pp. 136-145

Author(s):

Kaustubh Patil ◽

Kiran Seth ◽

Frank Mueller

Keyword(s):

Instruction Cache ◽

Cache Simulation

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Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis

2007 International Symposium on Industrial Embedded Systems ◽

10.1109/sies.2007.4297313 ◽

2007 ◽

Author(s):

Fadia Nemer ◽

Hugues Casse ◽

Pascal Sainrat ◽

Ali Awada

Keyword(s):

Execution Time ◽

Task Instruction ◽

Instruction Cache ◽

Worst Case Execution Time ◽

Cache Analysis ◽

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Efficient instruction cache simulation and execution profiling with a threaded-code interpreter

Proceedings of the 29th conference on Winter simulation - WSC '97 ◽

10.1145/268437.268745 ◽

1997 ◽

Author(s):

Peter S. Magnusson

Keyword(s):

Instruction Cache ◽

Cache Simulation

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Scalable Fixed-Point Free Instruction Cache Analysis

2011 IEEE 32nd Real-Time Systems Symposium ◽

10.1109/rtss.2011.26 ◽

2011 ◽

Author(s):

Damien Hardy ◽

Benjamin Lesage ◽

Isabelle Puaut

Keyword(s):

Fixed Point ◽

Instruction Cache ◽

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