An Aging-Aware GPU Register File Design Based on Data Redundancy

IEEE Transactions on Computers ◽

10.1109/tc.2018.2849376 ◽

2019 ◽

Vol 68 (1) ◽

pp. 4-20 ◽

Author(s):

Alejandro Valero ◽

Francisco Candel ◽

Dario Suarez-Gracia ◽

Salvador Petit ◽

Julio Sahuquillo

Keyword(s):

Register File ◽

Data Redundancy ◽

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Active-Cycle Based Register File Design for Reduced Ports and Energy

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00299 ◽

2009 ◽

Vol 31 (2) ◽

pp. 299-308 ◽

Author(s):

Yu-Lai ZHAO ◽

Xian-Feng LI ◽

Dong TONG ◽

Han-Xin SUN ◽

Jie CHEN ◽

...

Keyword(s):

Register File ◽

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Performance-centric register file design for GPUs using racetrack memory

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2016.7427984 ◽

2016 ◽

Author(s):

Shuo Wang ◽

Yun Liang ◽

Chao Zhang ◽

Xiaolong Xie ◽

Guangyu Sun ◽

...

Keyword(s):

Register File ◽

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Fault tolerant register file design for MIPS AES-crypto microprocessor

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS) ◽

10.1109/icecs.2015.7440343 ◽

2015 ◽

Author(s):

Buse Ustaoglu ◽

Berna Ors Yalcin

Keyword(s):

Fault Tolerant ◽

Register File ◽

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Power-aware register assignment for large register file design

The Journal of Supercomputing ◽

10.1007/s11227-011-0633-1 ◽

2011 ◽

Vol 61 (3) ◽

pp. 719-742 ◽

Author(s):

Wann-Yun Shieh ◽

Bo-Syun Wang

Keyword(s):

Register File ◽

File Design ◽

Register Assignment

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TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2014.2334136 ◽

2015 ◽

Vol 23 (7) ◽

pp. 1196-1209 ◽

Author(s):

Na Gong ◽

Jinhui Wang ◽

Shixiong Jiang ◽

Ramalingam Sridhar

Keyword(s):

Register File ◽

Power Efficient ◽

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A Power Efficient Approach to Fault-Tolerant Register File Design

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.53 ◽

2008 ◽

Author(s):

Mojtaba Amiri-Kamalabad ◽

Seyed Ghassem Miremadi ◽

Mahdi Fazeli

Keyword(s):

Fault Tolerant ◽

Register File ◽

Power Efficient ◽

Efficient Approach ◽

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FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2019.2946808 ◽

2020 ◽

Vol 39 (10) ◽

pp. 2396-2409

Author(s):

Quan Deng ◽

Youtao Zhang ◽

Zhenyu Zhao ◽

Shuzheng Zhang ◽

Minxuan Zhang ◽

...

Keyword(s):

Register File ◽

Fine Grained ◽

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Energy-Delay Trade-Offs in Instruction Register File Design

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) ◽

10.1109/norchip.2018.8573504 ◽

2018 ◽

Author(s):

Joonas Multanen ◽

Heikki Kultala ◽

Pekka Jaaskelainen

Keyword(s):

Register File ◽

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A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2006.5 ◽

2006 ◽

Author(s):

Lushan Liu ◽

Ramalingam Sridhar ◽

Shambhu Upadhyaya

Keyword(s):

Fault Tolerance ◽

Register File ◽

File Design ◽

Resistive Defects

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A Low-Swing Strategy in Multi-port Register File Design

Recent Advances in Computer Science and Information Engineering - Lecture Notes in Electrical Engineering ◽

10.1007/978-3-642-25769-8_109 ◽

2012 ◽

pp. 787-793

Author(s):

Hao Yan ◽

Yan Liu ◽

Donghui Wang ◽

Chaohuan Hou

Keyword(s):

Register File ◽

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