21st International Conference on VLSI Design (VLSID 2008)

Program Committee

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.7 ◽

2008 ◽

Keyword(s):

Program Committee

Oversampling Analog-to-Digital Converter Design

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.130 ◽

2008 ◽

Cited By ~ 1

Author(s):

Shanthi Pavan ◽

Nagendra Krishnapura

Keyword(s):

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Converter Design

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.56 ◽

2008 ◽

Cited By ~ 2

Author(s):

Sriram Sambamurthy ◽

Jacob A. Abraham ◽

Raghuram S. Tupuri

Keyword(s):

Power Estimation ◽

Register Transfer Level ◽

Sequential Circuits ◽

Top Down ◽

Dynamic Power ◽

Register Transfer

Industry Standards from Accellera

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.123 ◽

2008 ◽

Cited By ~ 2

Author(s):

Shrenik Mehta

Keyword(s):

Industry Standards

A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.78 ◽

2008 ◽

Cited By ~ 2

Author(s):

Sounak Roy ◽

Swapna Banerjee

Keyword(s):

Sample And Hold

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.69 ◽

2008 ◽

Author(s):

S.A. Kannan ◽

N.S. Sreeram ◽

Bharadwaj S. Amrutur

Keyword(s):

Logic Block

NBTI Degradation: A Problem or a Scare?

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.43 ◽

2008 ◽

Cited By ~ 15

Author(s):

Kewal K. Saluja ◽

Shriram Vijayakumar ◽

Warin Sootkaneung ◽

Xaingning Yang

Variability-Tolerant Register-Transfer Level Synthesis

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.114 ◽

2008 ◽

Cited By ~ 4

Author(s):

Anish Muttreja ◽

Srivaths Ravi ◽

Niraj K. Jha

Keyword(s):

Register Transfer Level ◽

Register Transfer

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.112 ◽

2008 ◽

Author(s):

Sabyasachi Das ◽

Sunil P. Khatri

Keyword(s):

Synthesis Technique ◽

Sum Of Products ◽

Fast Arithmetic

Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass

21st International Conference on VLSI Design (VLSID 2008) ◽

10.1109/vlsi.2008.116 ◽

2008 ◽

Cited By ~ 3

Author(s):

Kaushal R. Gandhi ◽

Nihar R. Mahapatra

Keyword(s):

Energy Efficient ◽

Soft Error ◽

Error Protection

21st International Conference on VLSI Design (VLSID 2008)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Program Committee

Oversampling Analog-to-Digital Converter Design

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

Industry Standards from Accellera

A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

NBTI Degradation: A Problem or a Scare?

Variability-Tolerant Register-Transfer Level Synthesis

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters

Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass

Export Citation Format

21st International Conference on VLSI Design (VLSID 2008)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Program Committee

Oversampling Analog-to-Digital Converter Design

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

Industry Standards from Accellera

A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

NBTI Degradation: A Problem or a Scare?

Variability-Tolerant Register-Transfer Level Synthesis

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters

Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass

21st International Conference on VLSI Design (VLSID 2008)
Latest Publications