A Threshold-Based Min-Sum Algorithm to Lower the Error Floors of Quantized LDPC Decoders

2020 ◽  
Vol 68 (4) ◽  
pp. 2005-2015
Author(s):  
Homayoon Hatami ◽  
David G. M. Mitchell ◽  
Daniel J. Costello ◽  
Thomas E. Fuja
Keyword(s):  
Error Floors

Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors

2011 ◽  
Vol E94-B (8) ◽  
pp. 2375-2377 ◽  
Author(s):  
Beomkyu SHIN ◽  
Hosung PARK ◽  
Jong-Seon NO ◽  
Habong CHUNG
Keyword(s):  
Ldpc Codes ◽  
Post Processing ◽  
Multi Stage ◽  
Error Floors

Analysis of error floors of LDPC codes under LP decoding over the BSC

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Author(s):  
Shashi Kiran Chilappagari ◽  
Bane Vasic ◽  
Mikhail Stepanov ◽  
Michael Chertkov
Keyword(s):  
Ldpc Codes ◽  
Error Floors ◽  
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Variable-Weight Block Dual-Diagonal Structure for Low-Rate QC LDPC Codes With Low Error Floors

2020 ◽  
Vol 68 (3) ◽  
pp. 1344-1357
Author(s):  
Hosung Park ◽  
Hee-Youl Kwak ◽  
Seokbeom Hong ◽  
Jong-Seon No ◽  
Dong-Joon Shin
Keyword(s):  
Ldpc Codes ◽  
Variable Weight ◽  
Error Floors ◽  
Low Rate

Lowering Error Floors of Irregular LDPC Codes by Combining Construction and Decoding

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Vol E95-B (1) ◽  
pp. 271-274 ◽  
Author(s):  
Xiaopeng JIAO ◽  
Jianjun MU ◽  
Fan FANG ◽  
Rong SUN
Keyword(s):  
Ldpc Codes ◽  
Irregular Ldpc Codes ◽  
Error Floors

An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors

2010 ◽  
Vol 45 (4) ◽  
pp. 843-855 ◽  
Author(s):  
Zhengya Zhang ◽  
Venkat Anantharam ◽  
Martin J. Wainwright ◽  
Borivoje Nikolic
Keyword(s):  
Ldpc Decoder ◽  
Decoder Design ◽  
Error Floors
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