Iterative Interference Cancellation for Multi-Carrier Modulation in MIMO-DWT Downlink Transmission

The Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) scheme represents the dominant radio interface for broadband multicarrier communication systems. However, with insufficient Cyclic Prefixes (CP), Inter-Symbol Interference (ISI) and Inter-Carrier Interference (ICI) occur due to the time-varying multipath channel. This means that the performance of the system will be degraded. In this paper, we investigate the interference problem for a MIMO Discrete Wavelet Transform (MIMO-DWT) system under the effect of the downlink LTE channel. A Low-Density Parity-Check (LDPC) decoder is used to estimate the decoded signal. The proposed iterative algorithm uses the estimated decoded signal to compute the components required for ICI/ISI interference reduction. In this paper, Iterative Interference Cancellation (IIC) is employed to mitigate the effects of interference that contaminates the received signal due to multiple antenna transmission and a multipath channel. An equalizer with minimum mean square error is considered. We compare the performance of our proposed algorithm with the traditional MIMO-OFDM scheme in terms of bit error probability under insufficient CP. Simulation results verify that significant improvements are achieved by using IIC and MIMO-IIC for both systems.

Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks

Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.

LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW.