Automatic Scaling Procedures for Analog Design Reuse

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2006.883849 ◽

2006 ◽

Vol 53 (12) ◽

pp. 2539-2547 ◽

Author(s):

Alessandro Savio ◽

Luigi Colalongo ◽

Michele Quarantelli ◽

Zsolt M. Kovacs-Vajna

Keyword(s):

Design Reuse ◽

Analog Design ◽

Automatic Scaling

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Scaling Rules For Mos Analog Design Reuse

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. ◽

10.1109/mixdes.2006.1706603 ◽

2006 ◽

Author(s):

T. Levi ◽

N. Lewis ◽

J. Tomas ◽

P. Fouillat

Keyword(s):

Design Reuse ◽

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Resizing rules for MOS analog-design reuse

IEEE Design & Test of Computers ◽

10.1109/54.990442 ◽

2002 ◽

Vol 19 (2) ◽

pp. 50-58 ◽

Author(s):

C. Galup-Montoro ◽

M.C. Schneider ◽

R.M. Coitinho

Keyword(s):

Design Reuse ◽

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Scaling rules and parameter tuning procedure for analog design reuse in technology migration

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1329472 ◽

2004 ◽

Author(s):

A. Savio ◽

L. Colalongo ◽

Z.M. Kovacs-Vajna ◽

M. Quarantelli

Keyword(s):

Parameter Tuning ◽

Design Reuse ◽

Analog Design ◽

Technology Migration

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A Simple and Efficient Fuse-Trimming Circuit for Analog Design

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278016 ◽

2020 ◽

Author(s):

Xianjie Wan ◽

Lin Zhang ◽

Jia Liu ◽

Jun Liu ◽

Dongbing Fu

Keyword(s):

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ESD Analog Design

The ESD Handbook ◽

10.1002/9781119233091.ch13 ◽

2021 ◽

pp. 583-627

Keyword(s):

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A constraint redundancy elimination strategy to improve design reuse in parametric modeling

Computers in Industry ◽

10.1016/j.compind.2021.103460 ◽

2021 ◽

Vol 129 ◽

pp. 103460

Author(s):

Carmen González-Lluch ◽

Raquel Plumed ◽

David Pérez-López ◽

Pedro Company ◽

Manuel Contero ◽

...

Keyword(s):

Parametric Modeling ◽

Design Reuse ◽

Redundancy Elimination ◽

Constraint Redundancy ◽

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A precise CMOS mismatch model for analog design from weak to strong inversion

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328304 ◽

2004 ◽

Author(s):

T. Serrano-Gotarredona ◽

B. Linares-Barranco ◽

J. Velarde-Ramirez

Keyword(s):

Analog Design ◽

Strong Inversion

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Optimal software design reuse policies: A control theoretic approach

Information Systems Frontiers ◽

10.1007/s10796-013-9421-1 ◽

2013 ◽

Vol 17 (2) ◽

pp. 439-453 ◽

Author(s):

Monica Johar ◽

Vijay Mookerjee ◽

Suresh Sethi

Keyword(s):

Software Design ◽

Design Reuse ◽

Theoretic Approach

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Simple noise formulas for MOS analog design

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1205532 ◽

2003 ◽

Author(s):

A. Arnaud ◽

C. Galup-Montoro

Keyword(s):

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Automatic Scaling of Complex-Event Processing Applications in Eucalyptus

2012 IEEE 15th International Conference on Computational Science and Engineering ◽

10.1109/iccse.2012.14 ◽

2012 ◽

Author(s):

Irina Astrova ◽

Arne Koschel ◽

Marc Schaaf

Keyword(s):

Complex Event Processing ◽

Event Processing ◽

Automatic Scaling

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