Shared Last-Level Cache Management and Memory Scheduling for GPGPUs with Hybrid Main Memory

2018 ◽  
Vol 17 (4) ◽  
pp. 1-25
Author(s):  
Guan Wang ◽  
Chuanqi Zang ◽  
Lei Ju ◽  
Mengying Zhao ◽  
Xiaojun Cai ◽  
...  
Keyword(s):  
Main Memory ◽  
Cache Management ◽  
Memory Scheduling

Orchestrating Cache Management and Memory Scheduling for GPGPU Applications

2014 ◽  
Vol 22 (8) ◽  
pp. 1803-1814 ◽  
Author(s):  
Shuai Mu ◽  
Yandong Deng ◽  
Yubei Chen ◽  
Huaiming Li ◽  
Jianming Pan ◽  
...  
Keyword(s):  
Cache Management ◽  
Memory Scheduling

Shared last-level cache management for GPGPUs with hybrid main memory

2017 ◽  
Author(s):  
Guan Wang ◽  
Xiaojun Cai ◽  
Lei Ju ◽  
Chuanqi Zang ◽  
Mengying Zhao ◽  
...  
Keyword(s):  
Main Memory ◽  
Cache Management

Write-back aware shared last-level cache management for hybrid main memory

2016 ◽  
Author(s):  
Deshan Zhang ◽  
Lei Ju ◽  
Mengying Zhao ◽  
Xiang Gao ◽  
Zhiping Jia
Keyword(s):  
Main Memory ◽  
Cache Management

AgiMonitor: a remote database monitoring tool for main memory database

2014 ◽  
Author(s):  
Huazhuang Yao ◽  
Yongyan Wang ◽  
Shuai Wang ◽  
Kun Li ◽  
Chao Guo
Keyword(s):  
Main Memory ◽  
Monitoring Tool ◽  
Main Memory Database

A Scheme for Protecting Confidentiality of No-volatile Main Memory Based on Phase-Change Memory

2011 ◽  
Vol 34 (11) ◽  
pp. 2114-2120 ◽  
Author(s):  
Peng ZHAO ◽  
Long-Yun ZHU
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Main Memory ◽  
Change Memory

Intelligent download and cache management for interactive non-linear video

2012 ◽  
Vol 70 (2) ◽  
pp. 905-948 ◽  
Author(s):  
Britta Meixner ◽  
Jürgen Hoffmann
Keyword(s):  
Cache Management ◽  
Non Linear

Improving memory scheduling via processor-side load criticality information

2013 ◽  
Vol 41 (3) ◽  
pp. 84-95 ◽  
Author(s):  
Saugata Ghose ◽  
Hyodong Lee ◽  
José F. Martínez
Keyword(s):  
Side Load ◽  
Memory Scheduling

scholarly journals Efficient local locking for massively multithreaded in-memory hash-based operators

2021 ◽  
Author(s):  
Bashar Romanous ◽  
Skyler Windh ◽  
Ildar Absalyamov ◽  
Prerna Budhkar ◽  
Robert Halstead ◽  
...  
Keyword(s):  
Relational Databases ◽  
Aggregation Operators ◽  
Main Memory ◽  
Paradigm Shifts ◽  
Multithreaded Processors ◽  
Cache Hierarchies ◽  
Processor Architectures ◽  
Spatial Locality ◽  
Content Addressable Memories ◽  
Multi Core Processor

AbstractThe join and group-by aggregation are two memory intensive operators that are affecting the performance of relational databases. Hashing is a common approach used to implement both operators. Recent paradigm shifts in multi-core processor architectures have reinvigorated research into how the join and group-by aggregation operators can leverage these advances. However, the poor spatial locality of the hashing approach has hindered performance on multi-core processor architectures which rely on using large cache hierarchies for latency mitigation. Multithreaded architectures can better cope with poor spatial locality by masking memory latency with many outstanding requests. Nevertheless, the number of parallel threads, even in the most advanced multithreaded processors, such as UltraSPARC, is not enough to fully cover the main memory access latency. In this paper, we explore the hardware re-configurability of FPGAs to enable deeper execution pipelines that maintain hundreds (instead of tens) of outstanding memory requests across four FPGAs-drastically increasing concurrency and throughput. We present two end-to-end in-memory accelerators for the join and group-by aggregation operators using FPGAs. Both accelerators use massive multithreading to mask long memory delays of traversing linked-list data structures, while concurrently managing hundreds of thread states across four FPGAs locally. We explore how content addressable memories can be intermixed within our multithreaded designs to act as a synchronizing cache, which enforces locks and merges jobs together before they are written to memory. Throughput results for our hash-join operator accelerator show a speedup between 2$$\times $$ × and 3.4$$\times $$ × over the best multi-core approaches with comparable memory bandwidths on uniform and skewed datasets. The accelerator for the hash-based group-by aggregation operator demonstrates that leveraging CAMs achieves average speedup of 3.3$$\times $$ × with a best case of 9.4$$\times $$ × in terms of throughput over CPU implementations across five types of data distributions.

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