An integrated algorithm for memory allocation and assignment in high-level synthesis

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1145/513918.514072 ◽

2002 ◽

Author(s):

Jaewon Seo ◽

Taewhan Kim ◽

Preeti R. Panda

Keyword(s):

High Level Synthesis ◽

Memory Allocation ◽

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Memory allocation and mapping in high-level synthesis - an integrated approach

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2003.817116 ◽

2003 ◽

Vol 11 (5) ◽

pp. 928-938 ◽

Author(s):

Jaewon Seo ◽

Taewhan Kim ◽

P.R. Panda

Keyword(s):

Integrated Approach ◽

High Level Synthesis ◽

Memory Allocation ◽

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Nonvolatile memory allocation and hierarchy optimization for high-level synthesis

The 20th Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2015.7058999 ◽

2015 ◽

Author(s):

Shuangchen Li ◽

Ang Li ◽

Yongpan Liu ◽

Yuan Xie ◽

Huazhong Yang

Keyword(s):

Nonvolatile Memory ◽

High Level Synthesis ◽

Memory Allocation ◽

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An integrated algorithm for memory allocation and assignment in high-level synthesis

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1109/dac.2002.1012697 ◽

2002 ◽

Author(s):

Jaewon Seo ◽

Taewhan Kim ◽

P.R. Panda

Keyword(s):

High Level Synthesis ◽

Memory Allocation ◽

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A Dynamic Memory Allocation Library for High-Level Synthesis

2019 29th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2019.00057 ◽

2019 ◽

Author(s):

Nicholas V. Giamblanco ◽

Jason H. Anderson

Keyword(s):

High Level Synthesis ◽

Memory Allocation ◽

Dynamic Memory ◽

Dynamic Memory Allocation ◽

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

High Level Synthesis ◽

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

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Exact and Practical Modulo Scheduling for High-Level Synthesis

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/3317670 ◽

2019 ◽

Vol 12 (2) ◽

pp. 1-26 ◽

Author(s):

Julian Oppermann ◽

Melanie Reuter-Oppermann ◽

Lukas Sommer ◽

Andreas Koch ◽

Oliver Sinnen

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

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