Wire Sizing

Handbook of Algorithms for Physical Design Automation ◽

10.1201/9781420013481-29 ◽

2008 ◽

pp. 585-596

Author(s):

Sanghamitra Roy ◽

Charlie Chung-Ping Chen

Keyword(s):

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Simultaneous wire sizing and wire spacing in post-layout performance optimization

Proceedings of 1998 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1998.669503 ◽

2002 ◽

Author(s):

Jiang-An He ◽

H. Kobayashi

Keyword(s):

Performance Optimization ◽

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Wire Sizing and Spacing for Lithographic Printability and Timing Optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2007.909807 ◽

2007 ◽

Vol 15 (12) ◽

pp. 1332-1340 ◽

Author(s):

Ke Cao ◽

Jiang Hu ◽

Mosong Cheng

Keyword(s):

Timing Optimization ◽

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Wire Sizing

Encyclopedia of Algorithms ◽

10.1007/978-1-4939-2864-4_483 ◽

2016 ◽

pp. 2374-2378

Author(s):

Chris Chu

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A sequential quadratic programming approach to concurrent gate and wire sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.644611 ◽

1997 ◽

Vol 16 (8) ◽

pp. 867-881 ◽

Author(s):

N. Menezes ◽

R. Baldick ◽

L.T. Pileggi

Keyword(s):

Quadratic Programming ◽

Sequential Quadratic Programming ◽

Programming Approach ◽

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PV wire sizing examples

Photovoltaic Systems and the National Electric Code ◽

10.4324/9781315110301-13 ◽

2018 ◽

pp. 189-197

Author(s):

Bill Brooks ◽

Sean White

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Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1145/288548.289097 ◽

1998 ◽

Author(s):

Chung-Ping Chen ◽

Chris C. N. Chu ◽

D. F. Wong

Keyword(s):

Lagrangian Relaxation ◽

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An efficient and optimal algorithm for simultaneous buffer and wire sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.784121 ◽

1999 ◽

Vol 18 (9) ◽

pp. 1297-1304 ◽

Author(s):

C.C.N. Chu ◽

D.F. Wong

Keyword(s):

Optimal Algorithm ◽

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Wire-sizing for delay minimization and ringing control using transmission line model

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) ◽

10.1109/date.2000.840833 ◽

2002 ◽

Author(s):

Youxin Gao ◽

D.F. Wong

Keyword(s):

Transmission Line ◽

Transmission Line Model ◽

Delay Minimization ◽

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Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004. ◽

10.1109/icecs.2004.1399707 ◽

2005 ◽

Author(s):

S. Greenberg ◽

I. Bloch ◽

M. Horwitz ◽

A. Maman

Keyword(s):

Wire Sizing ◽

Tree Performance

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Wire sizing and spacing for lithographic printability optimization

10.1117/12.708974 ◽

2007 ◽

Author(s):

Ke Cao ◽

Jiang Hu ◽

Mosong Cheng

Keyword(s):

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