Instruction scheduling and software pipelining for modern architectures

Proceedings of the Institute for System Programming of RAS ◽

10.15514/ispras-2012-22-2 ◽

2012 ◽

Vol 22 ◽

pp. 19-32

Author(s):

Arutyun Avetisyan

Keyword(s):

Instruction Scheduling ◽

Software Pipelining

Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00127 ◽

2009 ◽

Vol 31 (1) ◽

pp. 127-132

Author(s):

Zhi-Xiong ZHOU ◽

Hu HE ◽

Xu YANG ◽

Yan-Jun ZHANG ◽

Yi-He SUN

Keyword(s):

Scheduling Algorithm ◽

Instruction Scheduling ◽

Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings. ◽

10.1109/micro.2002.1176244 ◽

2003 ◽

Cited By ~ 6

Author(s):

E. Gibert ◽

J. Sanchez ◽

A. Gonzalez

Keyword(s):

Effective Instruction ◽

Instruction Scheduling ◽

Vliw Processor

The Marion system for retargetable instruction scheduling

Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation - PLDI '91 ◽

10.1145/113445.113465 ◽

1991 ◽

Cited By ~ 22

Author(s):

David G. Bradlee ◽

Robert R. Henry ◽

Susan J. Eggers

Keyword(s):

Instruction Scheduling

Integrating register allocation and instruction scheduling for RISCs

ACM SIGPLAN Notices ◽

10.1145/106973.106986 ◽

1991 ◽

Vol 26 (4) ◽

pp. 122-131 ◽

Cited By ~ 3

Author(s):

David G. Bradlee ◽

Susan J. Eggers ◽

Robert R. Henry

Keyword(s):

Instruction Scheduling

The Marion system for retargetable instruction scheduling

ACM SIGPLAN Notices ◽

10.1145/113446.113465 ◽

1991 ◽

Vol 26 (6) ◽

pp. 229-240 ◽

Cited By ~ 5

Author(s):

David G. Bradlee ◽

Robert R. Henry ◽

Susan J. Eggers

Keyword(s):

Instruction Scheduling

Speculation techniques for improving load related instruction scheduling

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) ◽

10.1109/isca.1999.765938 ◽

2003 ◽

Cited By ~ 54

Author(s):

A. Yoaz ◽

M. Erez ◽

R. Ronen ◽

S. Jourdan

Keyword(s):

Instruction Scheduling

Instruction scheduling using MAX-MIN ant system optimization

Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05 ◽

10.1145/1057661.1057674 ◽

2005 ◽

Cited By ~ 4

Author(s):

Gang Wang ◽

Wenrui Gong ◽

Ryan Kastner

Keyword(s):

System Optimization ◽

Instruction Scheduling ◽

Ant System

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques

International Symposium on System Synthesis (IEEE Cat. No.01EX526) ◽

10.1145/500001.500052 ◽

2001 ◽

Cited By ~ 5

Author(s):

Noureddine Chabini ◽

Yvon Savaria

Keyword(s):

Software Pipelining ◽

Synchronous Circuits

Guiding instruction scheduling with synchronisation markers on a superscalar based multiprocessor

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:19941519 ◽

1994 ◽

Vol 141 (6) ◽

pp. 398

Author(s):

R.-Y. Hwang ◽

F. Lai

Keyword(s):

Instruction Scheduling

Register-sensitive software pipelining

Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing ◽

10.1109/ipps.1998.669910 ◽

2002 ◽

Cited By ~ 13

Author(s):

A.K. Dani ◽

V. Janaki Ramanan ◽

R. Govindarajan

Keyword(s):

Software Pipelining