2016 Formal Methods in Computer-Aided Design (FMCAD)
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[Front cover]

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886642 ◽

2016 ◽

Keyword(s):

Front Cover

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Program synthesis for networks

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886653 ◽

2016 ◽

Author(s):

Pavol Cerny

Keyword(s):

Program Synthesis

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2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886646 ◽

2016 ◽

Download Full-text

Routing under constraints

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886670 ◽

2016 ◽

Cited By ~ 3

Author(s):

Alexander Nadel

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Verifying hyperproperties of hardware systems

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886651 ◽

2016 ◽

Author(s):

Bernd Finkbeiner ◽

Markus Rabe

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A consistency checker for memory subsystem traces

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886671 ◽

2016 ◽

Cited By ~ 1

Author(s):

Matthew Naylor ◽

Simon W. Moore ◽

Alan Mujumdar

Keyword(s):

Memory Subsystem

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Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886657 ◽

2016 ◽

Cited By ~ 1

Author(s):

G. Cabodi ◽

P. E. Camurati ◽

M. Palena ◽

P. Pasini ◽

D. Vendraminetto

Keyword(s):

Ad Hoc ◽

Logic Synthesis

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Formal verification of division and square root implementations, an Oracle report

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886673 ◽

2016 ◽

Cited By ~ 2

Author(s):

David L. Rager ◽

Jo Ebergen ◽

Dmitry Nadezhin ◽

Austin Lee ◽

Cuong Kim Chau ◽

...

Keyword(s):

Formal Verification ◽

Square Root

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[Copyright notice]

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886643 ◽

2016 ◽

Keyword(s):

Download Full-text

Machine learning and systems for the next frontier in formal verification

2016 Formal Methods in Computer-Aided Design (FMCAD) ◽

10.1109/fmcad.2016.7886650 ◽

2016 ◽

Cited By ~ 2

Author(s):

Manish Pandey

Keyword(s):

Machine Learning ◽

Formal Verification

Download Full-text

2016 Formal Methods in Computer-Aided Design (FMCAD)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

[Front cover]

Program synthesis for networks

Table of contents

Routing under constraints

Verifying hyperproperties of hardware systems

A consistency checker for memory subsystem traces

Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening

Formal verification of division and square root implementations, an Oracle report

[Copyright notice]

Machine learning and systems for the next frontier in formal verification

Export Citation Format

2016 Formal Methods in Computer-Aided Design (FMCAD)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

[Front cover]

Program synthesis for networks

Table of contents

Routing under constraints

Verifying hyperproperties of hardware systems

A consistency checker for memory subsystem traces

Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening

Formal verification of division and square root implementations, an Oracle report

[Copyright notice]

Machine learning and systems for the next frontier in formal verification

2016 Formal Methods in Computer-Aided Design (FMCAD)
Latest Publications