Network-on-a-chip of a new microprocessor generation with the Elbrus architecture

The paper describes a network-on-chip of a new microprocessor generation with the Elbrus architecture, taking into account the peculiarities of physical design. The network-on-a-chip under consideration plays a central role in the scaling process of the microprocessor, interconnecting all the main components of the system and ensuring the transfer of all types of packets between devices. The characteristics of the network-on-a-chip determine the bandwidth and access time to the memory subsystem.

ОПТИМИЗАЦИЯ МЕХАНИЗМА БУФЕРИЗАЦИИ ЗАПРОСОВ В КЕШ-ПАМЯТИ ВТОРОГО УРОВНЯ

Рассмотрен метод повышения производительности подсистемы памяти суперскалярного RISC-микропроцессора путем модернизации буфера предварительного считывания в составе кеш-памяти второго уровня. Приведены результаты моделирования поведенческой модели микропроцессора, результаты сравнения с предыдущей модификацией, показавшие эффективность введенных изменений. A method of improving the memory subsystem of a superscalar RISC micropocessor through the modernization of the pre-read buffer as part of the second-level cache memory is considered. The results of modeling the microprocessor behavioral model, the results of comparison with the previous modification are presented. The paper shows the effectiveness of the introduced changes.

Addressing multi-bit errors in DRAM/memory subsystem

As DRAM technology continues to evolve towards smaller feature sizes and increased densities, faults in DRAM subsystem are becoming more severe. Current servers mostly use CHIPKILL based schemes to tolerate up-to one/two symbol errors per DRAM beat. Such schemes may not detect multi-symbol errors arising due to faults in multiple data buses and/or chips. In this work, we introduce Single Symbol Correction Multiple Symbol Detection (SSCMSD) - a novel error handling scheme to correct single-symbol errors and detect multi-symbol errors. Our scheme makes use of a hash in combination with Error Correcting Code (ECC) to avoid silent data corruptions (SDCs). SSCMSD also enhances the capability of detecting errors in address bits. We develop a novel scheme that deploys 32-bit CRC along with Reed-Solomon code to implement SSCMSD for a x4 based DDRx system. Simulation based experiments show that our scheme effectively prevents SDCs in the presence of multi-symbol errors (in data) as well as address bit errors only limited by the aliasing probability of the hash. Our novel design enabled us to achieve this without introducing additional READ latency. We need 19 chips per rank (storage overhead of 18.75 percent), 76 data bus-lines and additional hash-logic at the memory controller.