Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.
Latest Publications

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(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769520618

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Fast indexing for blocked array layouts to improve multi-level cache locality

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299515 ◽

2004 ◽

Cited By ~ 8

Author(s):

E. Athanasaki ◽

N. Koziris

Keyword(s):

Multi Level

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Link-time optimization techniques for eliminating conditional branch redundancies

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299513 ◽

2004 ◽

Cited By ~ 1

Author(s):

M. Fernandez ◽

R. Espasa

Keyword(s):

Optimization Techniques ◽

Time Optimization ◽

Conditional Branch

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Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299505 ◽

2004 ◽

Author(s):

Youfeng Wu ◽

M. Breternitz ◽

T. Devor

Keyword(s):

Two Phase ◽

Phase Dynamic ◽

Loop Optimizations

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Garbage collector re .nement for new dynamic multimedia applications on embedded systems

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299507 ◽

2004 ◽

Author(s):

J.M. Velasco ◽

D. Atienza ◽

F. Catthoor ◽

F. Tirado ◽

K. Olcoz ◽

...

Keyword(s):

Embedded Systems ◽

Multimedia Applications ◽

Garbage Collector

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Exploitation of instruction-level parallelism for optimal loop scheduling

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299506 ◽

2004 ◽

Cited By ~ 2

Author(s):

J. Muller ◽

D. Fimmel ◽

R. Merker

Keyword(s):

Instruction Level Parallelism ◽

Loop Scheduling ◽

Level Parallelism

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Exploiting procedure level locality to reduce instruction cache misses

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299512 ◽

2004 ◽

Author(s):

R.V. Batchu ◽

D.A. Jimenez

Keyword(s):

Instruction Cache

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Energy-ef .ciency potential of a phase-based cache resizing scheme for embedded systems

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299510 ◽

2004 ◽

Author(s):

G. Pokam ◽

F. Bodin

Keyword(s):

Embedded Systems ◽

Cache Resizing

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Cool-fetch: a compiler-enabled IPC estimation based framework for energy reduction

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299509 ◽

2004 ◽

Cited By ~ 3

Author(s):

O.S. Unsal ◽

I. Koren ◽

C.M. Krishna ◽

C.A. Moritz

Keyword(s):

Energy Reduction

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Data movement optimization for software-controlled on-chip memory

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299516 ◽

2004 ◽

Cited By ~ 1

Author(s):

M. Fujita ◽

M. Kondo ◽

H. Nakamura

Keyword(s):

Data Movement ◽

On Chip

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Simsnap: fast-forwarding via native execution and application-level checkpointing

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. ◽

10.1109/intera.2004.1299511 ◽

2004 ◽

Cited By ~ 6

Author(s):

P.K. Szwed ◽

D. Marques ◽

R.M. Buels ◽

S.A. McKee ◽

M. Schulz

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Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Fast indexing for blocked array layouts to improve multi-level cache locality

Link-time optimization techniques for eliminating conditional branch redundancies

Continuous trip count profiling for loop optimizations in two-phase dynamic binary translators

Garbage collector re .nement for new dynamic multimedia applications on embedded systems

Exploitation of instruction-level parallelism for optimal loop scheduling

Exploiting procedure level locality to reduce instruction cache misses

Energy-ef .ciency potential of a phase-based cache resizing scheme for embedded systems

Cool-fetch: a compiler-enabled IPC estimation based framework for energy reduction

Data movement optimization for software-controlled on-chip memory

Simsnap: fast-forwarding via native execution and application-level checkpointing

Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.
Latest Publications