Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
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Published By Springer Netherlands

9781402048258

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Case study

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_9 ◽

2006 ◽

pp. 141-152

Classification of platform elements

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_3 ◽

2006 ◽

pp. 15-32

Summary

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_10 ◽

2006 ◽

pp. 153-157

Unified timing model

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_7 ◽

2006 ◽

pp. 79-112

Keyword(s):

Timing Model

MP-SOC simulation framework

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_8 ◽

2006 ◽

pp. 113-139

Keyword(s):

Simulation Framework

Related work

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_5 ◽

2006 ◽

pp. 43-58

System level design principles

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_4 ◽

2006 ◽

pp. 33-42

Keyword(s):

Design Principles ◽

System Level ◽

System Level Design ◽

Level Design

Embedded SOC applications

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_2 ◽

2006 ◽

pp. 9-14

Keyword(s):

Embedded Soc

Introduction

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_1 ◽

2006 ◽

pp. 1-7

Methodology overview

Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms ◽

10.1007/1-4020-4826-2_6 ◽

2006 ◽

pp. 59-77