IEEE Computer Architecture Letters
Latest Publications

TOTAL DOCUMENTS

593

(FIVE YEARS 86)

H-INDEX

32

(FIVE YEARS 2)

Published By Institute Of Electrical And Electronics Engineers

1556-6064, 1556-6056

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3098943 ◽

2021 ◽

Vol 20 (2) ◽

pp. 118-121

Author(s):

Yunjae Lee ◽

Youngeun Kwon ◽

Minsoo Rhu

Keyword(s):

Neural Network ◽

Large Scale ◽

Neural Network Training ◽

Network Training ◽

Non Volatile Memory ◽

Volatile Memory

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2020 Index IEEE Computer Architecture Letters Vol. 19

IEEE Computer Architecture Letters ◽

10.1109/lca.2020.3048555 ◽

2021 ◽

Vol 20 (1) ◽

pp. 1-7

Keyword(s):

Computer Architecture

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Hy-Sched: A Simple Hyperthreading-Aware Thread to Core Allocation Strategy

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3051393 ◽

2021 ◽

Vol 20 (1) ◽

pp. 26-29

Author(s):

Marta Navarro ◽

Lucia Pons ◽

Julio Sahuquillo

Keyword(s):

Allocation Strategy ◽

Core Allocation

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Chopping Off the Tail: Bounded Non-Determinism for Real-Time Accelerators

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3102224 ◽

2021 ◽

pp. 1-1

Author(s):

Alexander C Rucker ◽

Muhammad Shahbaz ◽

Kunle Olukotun

Keyword(s):

Real Time

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Instruction Criticality based Energy-efficient Hardware Data Prefetching

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3117005 ◽

2021 ◽

pp. 1-1

Author(s):

Neelu Shivprakash Kalani ◽

Biswabandan Panda

Keyword(s):

Energy Efficient ◽

Data Prefetching

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Data-Aware Compression of Neural Networks

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3096191 ◽

2021 ◽

pp. 1-1

Author(s):

Hajar Falahati ◽

Masoud Peyro ◽

Hossein Amini ◽

Mehran Taghian ◽

Mohammad Sadrosadati ◽

...

Keyword(s):

Neural Networks

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Zero-copying I/O Stack for Low-latency SSDs

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3064876 ◽

2021 ◽

pp. 1-1

Author(s):

Sunghwan Kim ◽

Gyusun Lee ◽

Jiwon Woo ◽

Jinkyu Jeong

Keyword(s):

Low Latency

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STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3097253 ◽

2021 ◽

pp. 1-1

Author(s):

Francisco Munoz-Martinez ◽

Jose Abellan ◽

Manuel E. Acacio ◽

Tushar Krishna

Keyword(s):

Microarchitectural Simulation

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Near-Data Processing in Memory Expander for DNN Acceleration on GPUs

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3126450 ◽

2021 ◽

pp. 1-1

Author(s):

Hyungkyu Ham ◽

Hyunuk Cho ◽

Minjae Kim ◽

Jueon Park ◽

Jeongmin Hong ◽

...

Keyword(s):

Data Processing

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Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions

IEEE Computer Architecture Letters ◽

10.1109/lca.2021.3123408 ◽

2021 ◽

pp. 1-1

Author(s):

Pavlos Aimoniotis ◽

Christos Sakalis ◽

Magnus Sjalander ◽

Stefanos Kaxiras

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