2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Latest Publications

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Published By IEEE

9781728119687

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641732 ◽

2018 ◽

Cited By ~ 8

Author(s):

Ievgen Kabin ◽

Dan Kreiser ◽

Zoya Dyka ◽

Peter Langendoerfer

Keyword(s):

Low Cost ◽

Fpga Implementation

An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641735 ◽

2018 ◽

Cited By ~ 3

Author(s):

Ahmed M. Abdelsalam ◽

Felix Boulet ◽

Gabriel Demers ◽

J. M. Pierre Langlois ◽

Farida Cheriet

Keyword(s):

Fully Connected

LaKe: The Power of In-Network Computing

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641696 ◽

2018 ◽

Cited By ~ 5

Author(s):

Yuta Tokusashi ◽

Hiroki Matsutani ◽

Noa Zilberman

Keyword(s):

Network Computing

MBSS:A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641701 ◽

2018 ◽

Author(s):

Shuai Xie ◽

Zhongyuan Zhao ◽

Weiguang Sheng ◽

Qin Wang ◽

Zhigang Mao

Keyword(s):

Nested Loops ◽

Static Schedule

A Highly Parallel FPGA Implementation of Sparse Neural Network Training

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641739 ◽

2018 ◽

Cited By ~ 2

Author(s):

Sourya Dey ◽

Diandian Chen ◽

Zongyang Li ◽

Souvik Kundu ◽

Kuan-Wen Huang ◽

...

Keyword(s):

Neural Network ◽

Fpga Implementation ◽

Neural Network Training ◽

Network Training

Flexible FPGA ECDSA Design with a Field Multiplier Inherently Resistant against HCCA

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641730 ◽

2018 ◽

Author(s):

Zoya Dyka ◽

Dan Kreiser ◽

Ievgen Kabin ◽

Peter Langendoerfer

Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641698 ◽

2018 ◽

Author(s):

Dillon Huff ◽

Pat Hanrahan

Keyword(s):

Reconfigurable Architectures

An FPGA-based Hardware Accelerator for Iris Segmentation

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641726 ◽

2018 ◽

Cited By ~ 1

Author(s):

Joe Avey ◽

Phillip Jones ◽

Joseph Zambreno

Keyword(s):

Hardware Accelerator ◽

Iris Segmentation

ReConFig 2018 Keynote 1 - FPGAs at HyperScale - The Past, Present, and Future of the Reconfigurable Cloud

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641728 ◽

2018 ◽

Keyword(s):

The Past

Configuration Tampering of BRAM-based AES Implementations on FPGAs

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2018.8641692 ◽

2018 ◽

Author(s):

Daniel Ziener ◽

Jutta Pirkl ◽

Jirgen Teich

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA

An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs

LaKe: The Power of In-Network Computing

MBSS:A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs

A Highly Parallel FPGA Implementation of Sparse Neural Network Training

Flexible FPGA ECDSA Design with a Field Multiplier Inherently Resistant against HCCA

Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures

An FPGA-based Hardware Accelerator for Iris Segmentation

ReConFig 2018 Keynote 1 - FPGAs at HyperScale - The Past, Present, and Future of the Reconfigurable Cloud

Configuration Tampering of BRAM-based AES Implementations on FPGAs

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Latest Publications