Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology
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Published By Springer US

9781504128858, 9780387351902

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Efficient CTL* Model Checking for Analysis of Rainbow Designs

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_9 ◽

1997 ◽

pp. 128-145 ◽

Cited By ~ 2

Author(s):

W. Visser ◽

H. Barringer ◽

D. Fellows ◽

G. Gough ◽

A. Williams

Keyword(s):

Model Checking

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Verifying Out-of-Order Executions

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_3 ◽

1997 ◽

pp. 23-47 ◽

Cited By ~ 14

Author(s):

W. Damm ◽

A. Pnueli

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Using induction and BDDs to model check invariants

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_13 ◽

1997 ◽

pp. 203-213 ◽

Cited By ~ 3

Author(s):

David Déharbe ◽

Anamaria Martins Moreira

Keyword(s):

Model Check

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ASIC/System Hardware Verification at Nortel: A View from the Trenches

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_1 ◽

1997 ◽

pp. 1-1 ◽

Cited By ~ 1

Author(s):

A. Silburt

Keyword(s):

Hardware Verification

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A Polymodal Semantics for VHDL

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_6 ◽

1997 ◽

pp. 88-105 ◽

Cited By ~ 2

Author(s):

Subash Shankar ◽

James Slagle

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Formal Modeling and Validation Applied to a Commercial Coherent Bus: A Case Study

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_4 ◽

1997 ◽

pp. 48-62 ◽

Cited By ~ 3

Author(s):

Ganesh Gopalakrishnan ◽

Rajnish Ghughal ◽

Ravi Hosabettu ◽

Abdelillah Mokkedem ◽

Ratan Nalumasu

Keyword(s):

Formal Modeling

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Panel Discussion: Is There a Crisis in Hardware Verification?

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_20 ◽

1997 ◽

pp. 309-310

Author(s):

Hon F. Li ◽

David K. Probst

Keyword(s):

Panel Discussion ◽

Hardware Verification

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Automatic Post-Synthesis Verification Support for a High Level Synthesis Step by using the HOL Theorem Proving System

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_19 ◽

1997 ◽

pp. 291-308

Author(s):

Matthias Mutz

Keyword(s):

Theorem Proving ◽

High Level Synthesis ◽

Post Synthesis ◽

High Level

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Simulation-Based Verification of Network Protocols Performance

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_16 ◽

1997 ◽

pp. 236-251

Author(s):

Mario Baldi ◽

Fulvio Corno ◽

Maurizio Rebaudengo ◽

Paolo Prinetto ◽

Matteo Sonza Reorda ◽

...

Keyword(s):

Network Protocols ◽

Simulation Based

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A Parallel Approach to Symbolic Traversal based on Set Partitioning

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_11 ◽

1997 ◽

pp. 167-184 ◽

Cited By ~ 1

Author(s):

G. Cabodi ◽

P. Camurati ◽

A. Lioy ◽

M. Poncino ◽

S. Quer

Keyword(s):

Set Partitioning

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Advances in Hardware Design and Verification - IFIP Advances in Information and Communication TechnologyLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer US

Efficient CTL* Model Checking for Analysis of Rainbow Designs

Verifying Out-of-Order Executions

Using induction and BDDs to model check invariants

ASIC/System Hardware Verification at Nortel: A View from the Trenches

A Polymodal Semantics for VHDL

Formal Modeling and Validation Applied to a Commercial Coherent Bus: A Case Study

Panel Discussion: Is There a Crisis in Hardware Verification?

Automatic Post-Synthesis Verification Support for a High Level Synthesis Step by using the HOL Theorem Proving System

Simulation-Based Verification of Network Protocols Performance

A Parallel Approach to Symbolic Traversal based on Set Partitioning

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology
Latest Publications