FPGA implementation of AES algorithm for high throughput using folded parallel architecture

K. Rahimunnisa; P. Karthigaikumar; Soumiya Rasheed; J. Jayakumar; S. SureshKumar

doi:10.1002/sec.651

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Security and Communication Networks ◽

10.1002/sec.651 ◽

2012 ◽

Vol 7 (11) ◽

pp. 2225-2236 ◽

Cited By ~ 20

Author(s):

K. Rahimunnisa ◽

P. Karthigaikumar ◽

Soumiya Rasheed ◽

J. Jayakumar ◽

S. SureshKumar

Keyword(s):

High Throughput ◽

Parallel Architecture ◽

Fpga Implementation ◽

Aes Algorithm

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FPGA implementation of an efficient high-throughput sphere decoder for MIMO systems based on the smallest singular value threshold

2010 NASA/ESA Conference on Adaptive Hardware and Systems ◽

10.1109/ahs.2010.5546236 ◽

2010 ◽

Cited By ~ 1

Author(s):

Xiang Wu ◽

John S. Thompson

Keyword(s):

High Throughput ◽

Mimo Systems ◽

Fpga Implementation ◽

Singular Value ◽

Sphere Decoder ◽

Smallest Singular Value

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FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i48/97269 ◽

2016 ◽

Vol 9 (48) ◽

Cited By ~ 1

Author(s):

Sandeep Kakde ◽

Atish Khobragade ◽

M. D. Ekbal Husain

Keyword(s):

High Throughput ◽

Ldpc Codes ◽

Fpga Implementation ◽

Irregular Ldpc Codes

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FPGA Implementation of Parallel Transformative Approach in AES Algorithm

Information and Communication Technology for Competitive Strategies - Lecture Notes in Networks and Systems ◽

10.1007/978-981-13-0586-3_34 ◽

2018 ◽

pp. 333-340 ◽

Cited By ~ 1

Author(s):

Padma Prasada ◽

Sathisha ◽

Ajay Prinston Pinto ◽

H. D. Ranjith

Keyword(s):

Fpga Implementation ◽

Aes Algorithm ◽

Transformative Approach

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FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

Microprocessors and Microsystems ◽

10.1016/j.micpro.2019.102972 ◽

2020 ◽

Vol 73 ◽

pp. 102972

Author(s):

S. Madhavapandian ◽

P. MaruthuPandi

Keyword(s):

Fpga Implementation ◽

Aes Algorithm ◽

Replacement Technique ◽

Security Application

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A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2019.2936260 ◽

2020 ◽

Vol 28 (1) ◽

pp. 101-114 ◽

Cited By ~ 1

Author(s):

Jin Woo Park ◽

Hyokeun Lee ◽

Boyeal Kim ◽

Dong-Goo Kang ◽

Seung Oh Jin ◽

...

Keyword(s):

Real Time ◽

High Throughput ◽

Low Cost ◽

Fpga Implementation ◽

Video Enhancement ◽

Retinex Algorithm

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High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping

Journal of Signal Processing Systems ◽

10.1007/s11265-008-0316-1 ◽

2008 ◽

Vol 57 (3) ◽

pp. 349-361 ◽

Cited By ~ 4

Author(s):

Camille Leroux ◽

Christophe Jégo ◽

Patrick Adde ◽

Michel Jézéquel

Keyword(s):

High Throughput ◽

Parallel Architecture ◽

Turbo Decoding

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High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2014.2332266 ◽

2014 ◽

Vol 61 (9) ◽

pp. 2699-2710 ◽

Cited By ~ 27

Author(s):

Rahul Shrestha ◽

Roy P. Paily

Keyword(s):

Wireless Communication ◽

High Throughput ◽

Parallel Architecture ◽

Turbo Decoder

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A WiMAX/LTE compliant FPGA implementation of a high-throughput low-complexity 4×4 64-QAM soft MIMO receiver

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2010.5757541 ◽

2010 ◽

Cited By ~ 2

Author(s):

Vadim Smolyakov ◽

Dimpesh Patel ◽

Mahdi Shabany ◽

P. Glenn Gulak

Keyword(s):

High Throughput ◽

Low Complexity ◽

Fpga Implementation

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High-Throughput FPGA Implementation of QR Decomposition

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2015.2435753 ◽

2015 ◽

Vol 62 (9) ◽

pp. 861-865 ◽

Cited By ~ 22

Author(s):

Sergio D. Munoz ◽

Javier Hormigo

Keyword(s):

High Throughput ◽

Qr Decomposition ◽

Fpga Implementation

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AES Algorithm Optimization and FPGA Implementation

IOP Conference Series Earth and Environmental Science ◽

10.1088/1755-1315/267/4/042070 ◽

2019 ◽

Vol 267 ◽

pp. 042070

Author(s):

Yufeng Liu ◽

Xiangyang Xu ◽

Hao Su

Keyword(s):

Fpga Implementation ◽

Algorithm Optimization ◽

Aes Algorithm

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