Live Range Aware Cache Architecture

2006 ◽  
pp. 409-415
Author(s):  
Peng Li ◽  
Dongsheng Wang ◽  
Songliu Guo ◽  
Tao Tian ◽  
Weimin Zheng
Keyword(s):  
Cache Architecture ◽  
Live Range

Selective-set-invalidation (SSI) for soft-error-resilient cache architecture

1999 ◽  
Vol 27 (3) ◽  
pp. 4-9
Author(s):  
Seung H. Hwang ◽  
Gwan S. Choi
Keyword(s):  
Soft Error ◽  
Error Resilient ◽  
Cache Architecture

An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory

2022 ◽  
Vol 21 (1) ◽  
pp. 1-22
Author(s):  
Dongsuk Shin ◽  
Hakbeom Jang ◽  
Kiseok Oh ◽  
Jae W. Lee
Keyword(s):  
Energy Consumption ◽  
Main Memory ◽  
Battery Life ◽  
Mobile Platforms ◽  
Total Energy Consumption ◽  
Efficient Manner ◽  
Hybrid Memory ◽  
Spatial Locality ◽  
Cache Architecture ◽  
Energy Delay Product

A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is expected to increase further with ever-growing demands for bandwidth and capacity. A hybrid memory system with both DRAM and PCM can be an attractive solution to provide additional capacity and reduce standby energy. Although providing much greater density than DRAM, PCM has longer access latency and limited write endurance to make it challenging to architect it for main memory. To address this challenge, this article introduces CAMP, a novel DRAM c ache a rchitecture for m obile platforms with P CM-based main memory. A DRAM cache in this environment is required to filter most of the writes to PCM to increase its lifetime, and deliver highest efficiency even for a relatively small-sized DRAM cache that mobile platforms can afford. To address this CAMP divides DRAM space into two regions: a page cache for exploiting spatial locality in a bandwidth-efficient manner and a dirty block buffer for maximally filtering writes. CAMP improves the performance and energy-delay-product by 29.2% and 45.2%, respectively, over the baseline PCM-oblivious DRAM cache, while increasing PCM lifetime by 2.7×. And CAMP also improves the performance and energy-delay-product by 29.3% and 41.5%, respectively, over the state-of-the-art design with dirty block buffer, while increasing PCM lifetime by 2.5×.

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology

2005 ◽  
pp. 345-358
Author(s):  
Amit Agarwal ◽  
Kaushik Roy ◽  
T. N. Vijaykumar
Keyword(s):  
Cache Architecture ◽  
High Bandwidth
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