Matrix-Based Programming Optimization for Improving Memory Hierarchy Performance on Imagine

2006 ◽  
pp. 782-793 ◽  
Author(s):  
Xuejun Yang ◽  
Jing Du ◽  
Xiaobo Yan ◽  
Yu Deng
Keyword(s):  
Memory Hierarchy ◽  
Memory Hierarchy Performance

scholarly journals Memory hierarchy performance measurement of commercial dual-core desktop processors

2008 ◽  
Vol 54 (8) ◽  
pp. 816-828 ◽  
Author(s):  
Lu Peng ◽  
Jih-Kwon Peir ◽  
Tribuvan K. Prakash ◽  
Carl Staelin ◽  
Yen-Kuang Chen ◽  
...  
Keyword(s):  
Performance Measurement ◽  
Memory Hierarchy ◽  
Memory Hierarchy Performance ◽  
Dual Core

MEMORY HIERARCHY PERFORMANCE PREDICTION FOR BLOCKED SPARSE ALGORITHMS

1999 ◽  
Vol 09 (03) ◽  
pp. 347-360 ◽  
Author(s):  
BASILIO B. FRAGUELA ◽  
RAMÓN DOALLO ◽  
EMILIO L. ZAPATA
Keyword(s):  
Sparse Matrix ◽  
Memory Hierarchy ◽  
Sparse Matrices ◽  
Main Memory ◽  
Matrix Product ◽  
Dense Matrix ◽  
Good Program ◽  
Compressed Storage ◽  
Access Patterns ◽  
Memory Hierarchy Performance

Nowadays the performance gap between processors and main memory makes an efficient usage of the memory hierarchy necessary for good program performance. Several techniques have been proposed for this purpose. Nevertheless most of them consider only regular access patterns, while many scientific and numerical applications give place to irregular patterns. A typical case is that of indirect accesses due to the use of compressed storage formats for sparse matrices. This paper describes an analytic approach to model both regular and irregular access patterns. The application modeled is an optimized sparse matrix-dense matrix product algorithm with several levels of blocking. Our model can be directly applied to any memory hierarchy consisting of K-way associative caches. Results are shown for several current microprocessor architectures.

Probabilistic miss equations: evaluating memory hierarchy performance

2003 ◽  
Vol 52 (3) ◽  
pp. 321-336 ◽  
Author(s):  
B.B. Fraguela ◽  
R. Doallo ◽  
E.L. Zapata
Keyword(s):  
Memory Hierarchy ◽  
Memory Hierarchy Performance

Tiling, block data layout, and memory hierarchy performance

2003 ◽  
Vol 14 (7) ◽  
pp. 640-654 ◽  
Author(s):  
Neungsoo Park ◽  
Bo Hong ◽  
V.K. Prasanna
Keyword(s):  
Memory Hierarchy ◽  
Data Layout ◽  
Block Data ◽  
Memory Hierarchy Performance

scholarly journals A compiler tool to predict memory hierarchy performance of scientific codes

2004 ◽  
Vol 30 (2) ◽  
pp. 225-248 ◽  
Author(s):  
B.B. Fraguela ◽  
R. Doallo ◽  
J. Touriño ◽  
E.L. Zapata
Keyword(s):  
Memory Hierarchy ◽  
Memory Hierarchy Performance
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