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Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors
Distributed Embedded Systems: Design, Middleware and Resources - IFIP – The International Federation for Information Processing
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10.1007/978-0-387-09661-2_11
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2008
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pp. 111-120
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Cited By ~ 1
Author(s):
Meng Wang
◽
Zili Shao
◽
Hui Liu
◽
Chun Jason Xue
Keyword(s):
Modulo Scheduling
◽
Vliw Dsp
◽
Dsp Processors
Download Full-text
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Cited By
References
Modulo scheduling for the TMS320C6x VLIW DSP architecture
ACM SIGPLAN Notices
◽
10.1145/315253.314427
◽
1999
◽
Vol 34
(7)
◽
pp. 28-34
◽
Cited By ~ 5
Author(s):
Eric Stotzer
◽
Ernst Leiss
Keyword(s):
Modulo Scheduling
◽
Dsp Architecture
◽
Vliw Dsp
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Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors
13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007)
◽
10.1109/rtcsa.2007.60
◽
2007
◽
Cited By ~ 4
Author(s):
Meng Wang
◽
Zili Shao
◽
Chun Jason Xue
◽
Edwin H.-M. Sha
Keyword(s):
Real Time
◽
Energy Minimization
◽
Loop Scheduling
◽
Vliw Dsp
◽
Dsp Processors
◽
Time Loop
Download Full-text
Assembly code conversion through pattern mapping between two VLIW DSP processors: a case study
6th International Conference on Signal Processing, 2002.
◽
10.1109/icosp.2002.1181076
◽
2003
◽
Cited By ~ 1
Author(s):
B. Su
◽
J. Wang
◽
E.W. Hu
◽
J. Manzano
Keyword(s):
Assembly Code
◽
Vliw Dsp
◽
Dsp Processors
Download Full-text
ORC2DSP: compiler infrastructure supports for VLIW DSP processors
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).
◽
10.1109/vdat.2005.1500062
◽
2005
◽
Author(s):
Cheng-Wei Chen
◽
Chung-Lin Tang
◽
Young-Chia Lin
◽
Jenq-Kuen Lee
Keyword(s):
Compiler Infrastructure
◽
Vliw Dsp
◽
Dsp Processors
Download Full-text
PALF: compiler supports for irregular register files in clustered VLIW DSP processors
Concurrency and Computation Practice and Experience
◽
10.1002/cpe.1176
◽
2007
◽
Vol 19
(18)
◽
pp. 2391-2406
◽
Cited By ~ 12
Author(s):
Yung-Chia Lin
◽
Yi-Ping You
◽
Jenq-Kuen Lee
Keyword(s):
Register Files
◽
Vliw Dsp
◽
Dsp Processors
Download Full-text
Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files
The Journal of Supercomputing
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10.1007/s11227-011-0671-8
◽
2011
◽
Vol 61
(3)
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pp. 1024-1047
◽
Cited By ~ 1
Author(s):
Chung-Ju Wu
◽
Yu-Te Lin
◽
Jenq-Kuen Lee
Keyword(s):
Instruction Scheduling
◽
Register Files
◽
Vliw Dsp
◽
Phase Ordering
◽
Dsp Processors
Download Full-text
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06)
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10.1109/rtcsa.2006.40
◽
2006
◽
Cited By ~ 2
Author(s):
Chi Wu
◽
Kun-Yuan Hsieh
◽
Yung-Chia Lin
◽
Chung-Ju Wu
◽
Wen-Li Shih
◽
...
Keyword(s):
Vliw Dsp
◽
Dsp Processors
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LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files
Concurrency and Computation Practice and Experience
◽
10.1002/cpe.1334
◽
2009
◽
Vol 21
(1)
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pp. 101-114
◽
Cited By ~ 11
Author(s):
Chia-Han Lu
◽
Yung-Chia Lin
◽
Yi-Ping You
◽
Jenq-Kuen Lee
Keyword(s):
Register File
◽
Register Files
◽
Vliw Dsp
◽
Dsp Processors
Download Full-text
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '07
◽
10.1145/1254766.1254793
◽
2007
◽
Cited By ~ 8
Author(s):
Chung-Kai Chen
◽
Ling-Hua Tseng
◽
Shih-Chang Chen
◽
Young-Jia Lin
◽
Yi-Ping You
◽
...
Keyword(s):
Register Files
◽
Vliw Dsp
◽
Dsp Processors
Download Full-text
An Efficient and Extendable Modeling Approach for VLIW DSP Processors
Communications in Computer and Information Science - Advances in Computer Science and Engineering
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10.1007/978-3-540-89985-3_33
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2008
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pp. 267-274
Author(s):
Naser Sedaghati-Mokhtari
◽
Mahdi Nazm-Bojnordi
◽
Abbas Hormati
◽
Sied Mehdi Fakhraie
Keyword(s):
Modeling Approach
◽
Vliw Dsp
◽
Dsp Processors
Download Full-text
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