Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files

2011 ◽  
Vol 61 (3) ◽  
pp. 1024-1047 ◽  
Author(s):  
Chung-Ju Wu ◽  
Yu-Te Lin ◽  
Jenq-Kuen Lee
Keyword(s):  
Instruction Scheduling ◽  
Register Files ◽  
Vliw Dsp ◽  
Phase Ordering ◽  
Dsp Processors

PALF: compiler supports for irregular register files in clustered VLIW DSP processors

2007 ◽  
Vol 19 (18) ◽  
pp. 2391-2406 ◽  
Author(s):  
Yung-Chia Lin ◽  
Yi-Ping You ◽  
Jenq-Kuen Lee
Keyword(s):  
Register Files ◽  
Vliw Dsp ◽  
Dsp Processors

Enabling compiler flow for embedded VLIW DSP processors with distributed register files

2007 ◽  
Vol 42 (7) ◽  
pp. 146-148 ◽  
Author(s):  
Chung-Kai Chen ◽  
Ling-Hua Tseng ◽  
Shih-Chang Chen ◽  
Young-Jia Lin ◽  
Yi-Ping You ◽  
...  
Keyword(s):  
Register Files ◽  
Vliw Dsp ◽  
Dsp Processors

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

2007 ◽  
Vol 51 (3) ◽  
pp. 269-288 ◽  
Author(s):  
Yung-Chia Lin ◽  
Chia Han Lu ◽  
Chung-Ju Wu ◽  
Chung-Lin Tang ◽  
Yi-Ping You ◽  
...  
Keyword(s):  
Code Generation ◽  
Ping Pong ◽  
Register Files ◽  
Vliw Dsp
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