Design and Implementation of a 32-bit Floating Point Unit

A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.

A Review on Hardware Accelerator Design and Implementation of CORDIC Algorithm for a Gaming Application

Co-ordinate Digital rotation computer is the full form of CORDIC.CORDIC is a process for finding functions using less hardware like shifts, subs/adds and then compares. It's the algorithm used for some elementary functions which are calculated in real-time and many conversions like from rectangular to polar co-ordinate and vice versa. Rectangular to polar and polar to rectangular is an important operation in CORDIC which are generally used in ALUs, wireless communications, DSP processors etc. This paper proposes the implementation of physical design for CORDIC algorithm for polar to rectangular and rectangular to polar conversions, by the use of RTL code in written in Verilog and fed to pre-processor, cordic core and post processor. This type of implementation results with greater efficiency, throughput by reducing power consumption and implanting it with high frequency. Hence due to great efficiency with low power it can be used for gaming applications.

Power-Based Non-Intrusive Condition Monitoring for Terminal Device in Smart Grid

As a critical component in the smart grid, the Distribution Terminal Unit (DTU) dynamically adjusts the running status of the entire smart grid based on the collected electrical parameters to ensure the safe and stable operation of the smart grid. However, as a real-time embedded device, DTU has not only resource constraints but also specific requirements on real-time performance, thus, the traditional anomaly detection method cannot be deployed. To detect the tamper of the program running on DTU, we proposed a power-based non-intrusive condition monitoring method that collects and analyzes the power consumption of DTU using power sensors and machine learning (ML) techniques, the feasibility of this approach is that the power consumption is closely related to the executing code in CPUs, that is when the execution code is tampered with, the power consumption changes accordingly. To validate this idea, we set up a testbed based on DTU and simulated four types of imperceptible attacks that change the code running in ARM and DSP processors, respectively. We generate representative features and select lightweight ML algorithms to detect these attacks. We finally implemented the detection system on the windows and ubuntu platform and validated its effectiveness. The results show that the detection accuracy is up to 99.98% in a non-intrusive and lightweight way.

DEVELOPMENT OF NOVEL ALGORITHM FOR HAAR TRANSFORM USING PAIRED TRANSFORM: IMPLEMENTATION ON TMS DSP PROCESSORS.

Paired transform splits the mathematical structure of many discrete unitary transforms, including the Fourier, Hadamard, Cosine and Hartley transforms, into the minimum number of short transforms. The discrete Haar transform that is very useful in many signal and image processing applications can be also calculated by the fast paired transform. The Haar transform can be considered as the particular case of the paired transforms, namely the 2-paired transform. In this research a Novel Fast algorithm for Haar transform is developed using paired transform: Paired Fast Haar Transform (Paired FHT). For illustration purposes relation between the Haar and paired transforms are described using the examples for 16, 8, 4 – point transforms are analyzed in detail. Finally the novel Haar transform: Paired Fast Haar transform is implemented using Code Compose Studio for TMS DSP processor Starter Kit (TMS DSK) TMS 320 C 6713 DSP processor for understanding the possible sampling rates.

Design of Area Efficent 32 Bit Arithmetic and Logic Unit (ALU) for DSP Processors

Almost every electronic gadget contains the Digital signal processor (DSP) unit for the purpose of computations, whose role couldn’t be specified with smaller words. Gadget’s performance, efficiency and the importance could be measured with how best the specifications of the processors are. Arithmetic and Logical Unit (ALU) is the key circuit for any DSP processors, where large data computations can be performed. Hence, the ALUs design should be include high performance and large data handling capacity. An ALU is a digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. The conventional ALU designs, design complexity rate proportionally increases with the performance demand. In this paper, an attempt has been given to design a low complex ALU with improved performance. Sub circuits designs comprise with new approaches to make the simple designs for higher performance of ALU. A 32 bit ALU design procedure has been demonstrated in this paper. For design, 90 nm CMOS technology and CADENCE virtuoso tools used.

Modern Rounding Based Approximate (MROBA) Multiplier for the Design of Fir Filter

For better power utilization,area,speed which are important criteria in the design of DSP processors multiplier design is main issue.The work of multiplier is rounding the numbers both signed and unsigned.In few applications speed is more important than accuracy so to improve the performance approximate circuits are introduced with reduce energy consumption and increase speed.In this paper,we propose an FIR filter based on Modern Rounding Based Approximate(M ROBA).In this modified rounding based approximate multiplier the numbers are rounded to the nearest exponent irrespective of 2 n .The proposed MROBA multiplier based FIR filter was compared with Rounding Based Approximate (ROBA) Multiplier. In this multiplier the operands are rounded to the nearest exponent of two. This approximation will lead to simplification of multiplication operation thus reducing area and increasing speed. MROBA gives better results with the MROBA MAC unit is implemented.

Design of modified booth based multiplier with carry pre-computation

Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

Wheelchairs Embedded Control System Design for Secure Navigation With RF Signal Triangulation

In the mobile robotic systems a precise estimate of the robot pose (Cartesian [x y] position plus orientation angle θ) with the intention of the path planning optimization is essential for the correct performance, on the part of the robots, for tasks that are destined to it, especially when intention is for mobile robot autonomous navigation. This work uses a ToF (Time-of-Flight) of the RF digital signal interacting with beacons for computational triangulation in the way to provide a pose estimative at bi-dimensional indoor environment, where GPS system is out of range. It's a new technology utilization making good use of old ultrasonic ToF methodology that takes advantage of high performance multicore DSP processors to calculate ToF of the order about ns. A mobile robot platform with differential drive and nonholonomic constraints is used as base for state space, plants and measurements models that are used in the simulations and for validation the experiments. After being tested and validated in the simulator, the control system is programmed in the control board memory of the mobile robot or wheelchair. Thus, the use of material is optimized, firstly validating the entire model virtually and afterwards operating the physical implementation of the navigation system.

Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors

Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.