Modulo scheduling for the TMS320C6x VLIW DSP architecture

ACM SIGPLAN Notices ◽

10.1145/315253.314427 ◽

1999 ◽

Vol 34 (7) ◽

pp. 28-34 ◽

Author(s):

Eric Stotzer ◽

Ernst Leiss

Keyword(s):

Modulo Scheduling ◽

Dsp Architecture ◽

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Modulo scheduling for the TMS320C6x VLIW DSP architecture

Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems - LCTES '99 ◽

10.1145/314403.314427 ◽

1999 ◽

Author(s):

Eric Stotzer ◽

Ernst Leiss

Keyword(s):

Modulo Scheduling ◽

Dsp Architecture ◽

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Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors

Distributed Embedded Systems: Design, Middleware and Resources - IFIP – The International Federation for Information Processing ◽

10.1007/978-0-387-09661-2_11 ◽

2008 ◽

pp. 111-120 ◽

Author(s):

Meng Wang ◽

Zili Shao ◽

Hui Liu ◽

Chun Jason Xue

Keyword(s):

Modulo Scheduling ◽

Vliw Dsp ◽

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An efficient VLIW DSP architecture for baseband processing

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240911 ◽

2004 ◽

Author(s):

Tay-Jyi Lin ◽

Chin-Chi Chang ◽

Chen-Chia Lee ◽

Chein-Wei Jen

Keyword(s):

Baseband Processing ◽

Dsp Architecture ◽

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Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture

ACM SIGPLAN Notices ◽

10.1145/384196.384216 ◽

2001 ◽

Vol 36 (8) ◽

pp. 138-144

Author(s):

Elana Granston ◽

Eric Stotzer ◽

Joe Zbiciak

Keyword(s):

Software Pipelining ◽

Dsp Architecture ◽

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Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture

Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems - OM '01 ◽

10.1145/384198.384216 ◽

2001 ◽

Author(s):

Elana Granston ◽

Eric Stotzer ◽

Joe Zbiciak

Keyword(s):

Software Pipelining ◽

Dsp Architecture ◽

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An efficient motion-adaption de-interlacing technique on VLIW DSP architecture

Proceedings. IEEE Conference on Advanced Video and Signal Based Surveillance, 2005. ◽

10.1109/avss.2005.1577344 ◽

2006 ◽

Author(s):

Cheng Peng ◽

Zhengting He ◽

Y. Cager

Keyword(s):

Dsp Architecture ◽

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Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools ◽

10.1109/dsd.2009.128 ◽

2009 ◽

Author(s):

Zheng Shen ◽

Hu He ◽

Yihe Sun

Keyword(s):

Simultaneous Multithreading ◽

Dsp Architecture ◽

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A low-cost VLIW DSP architecture for communication equipment

1998 URSI International Symposium on Signals Systems and Electronics Conference Proceedings (Cat No 98EX167) ISSSE-98 ◽

10.1109/issse.1998.738081 ◽

2002 ◽

Author(s):

L. Petit ◽

J.-D. Legat

Keyword(s):

Low Cost ◽

Dsp Architecture ◽

Vliw Dsp ◽

Communication Equipment

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Efficient Implementation of Givens QR Decomposition on VLIW DSP Architecture for Orthogonal Matching Pursuit Image Reconstruction

Lecture Notes in Electrical Engineering - Proceedings of the Mediterranean Conference on Information & Communication Technologies 2015 ◽

10.1007/978-3-319-30301-7_16 ◽

2016 ◽

pp. 147-155 ◽

Author(s):

Mohamed Najoui ◽

Anas Hatim ◽

Mounir Bahtat ◽

Said Belkouch

Keyword(s):

Image Reconstruction ◽

Matching Pursuit ◽

Qr Decomposition ◽

Efficient Implementation ◽

Orthogonal Matching Pursuit ◽

Dsp Architecture ◽

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High VelociTI processing [Texas Instruments VLIW DSP architecture]

IEEE Signal Processing Magazine ◽

10.1109/79.664702 ◽

1998 ◽

Vol 15 (2) ◽

pp. 86-101, 117 ◽

Author(s):

N. Seshan

Keyword(s):

Dsp Architecture ◽

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