Fault diagnosis has played an important role in the identification of fault mechanisms and the subsequent successful isolation of faults in electronic circuits. In this paper, we propose a novel procedure for fault diagnosis in analog circuits. We first generate a set of fault patterns from fault simulation, and our main task is to develop a practical description of the way in which these fault patterns interact. Our approach is based on the construction of a complex network that describes the inter-dependence of the various fault patterns. Analysis of this complex network shows that the degree distribution is scalefree-like and the connectivity is small-world. We henceforth identify a small number of fault patterns that are most highly connected (of highest degrees) with other fault patterns. Furthermore, we study the connection between this network of fault patterns and the original circuit, the purpose being to relate the information of the high-degree fault patterns with the physical circuit topology, thus allowing the physical fault locations and circuit elements to be identified. Our proposed approach will find applications in automatic fault diagnosis of large-scale electronic circuits.
Study on the Transducer Power Electronic Circuits Fault Diagnosis Based on SVM
