Proceedings of 9th International Conference on VLSI Design
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Science, Technology, and the Indian Society

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489443 ◽

2005 ◽

Author(s):

V.D. Agrawal

Keyword(s):

Indian Society ◽

Science Technology

Parallel concurrent path-delay fault simulation using single-input change patterns

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489647 ◽

2002 ◽

Cited By ~ 4

Author(s):

M.A. Gharaybeh ◽

M.L. Bushnell ◽

V.D. Agrawal

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Single Input

Design tradeoffs in high speed multipliers and FIR filters

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489449 ◽

2002 ◽

Cited By ~ 1

Author(s):

C. Nagendra ◽

R.M. Owens ◽

M.J. Irwin

Keyword(s):

High Speed ◽

Fir Filters ◽

Design Tradeoffs

An efficient test generation technique for sequential circuits with repetitive sub-circuits

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489480 ◽

2002 ◽

Author(s):

D.R. Chakrabarti ◽

A. Jain

Keyword(s):

Test Generation ◽

Sequential Circuits ◽

Generation Technique ◽

Efficient Test

Synchronous controller models for synthesis from communicating VHDL processes

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489484 ◽

2002 ◽

Cited By ~ 1

Author(s):

N. Narasimhan ◽

J. Roy ◽

R. Vemuri

Maximum power estimation for CMOS circuits using deterministic and statistic approaches

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489636 ◽

2002 ◽

Cited By ~ 13

Author(s):

Chuan-Yu Wang ◽

K. Roy

Keyword(s):

Power Estimation ◽

Maximum Power ◽

Cmos Circuits

A novel BIST architecture with built-in self check

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489455 ◽

2002 ◽

Author(s):

M.F. Abdulla ◽

C.P. Ravikumar ◽

A. Kumar

Node-covering based defect and fault tolerance methods for increased yield in FPGAs

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489489 ◽

2002 ◽

Cited By ~ 18

Author(s):

F. Hanchek ◽

S. Dutt

Keyword(s):

Fault Tolerance ◽

Node Covering

Design for high-speed testability of stuck-at faults

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489454 ◽

2002 ◽

Author(s):

T.J. Chakraborty ◽

V.D. Agrawal

Keyword(s):

High Speed

VaWiRAM: a variable width random access memory module

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489488 ◽

2002 ◽

Author(s):

L.K. John

Keyword(s):

Random Access ◽

Random Access Memory ◽

Access Memory ◽

Memory Module

Proceedings of 9th International Conference on VLSI DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Science, Technology, and the Indian Society

Parallel concurrent path-delay fault simulation using single-input change patterns

Design tradeoffs in high speed multipliers and FIR filters

An efficient test generation technique for sequential circuits with repetitive sub-circuits

Synchronous controller models for synthesis from communicating VHDL processes

Maximum power estimation for CMOS circuits using deterministic and statistic approaches

A novel BIST architecture with built-in self check

Node-covering based defect and fault tolerance methods for increased yield in FPGAs

Design for high-speed testability of stuck-at faults

VaWiRAM: a variable width random access memory module

Proceedings of 9th International Conference on VLSI Design
Latest Publications