scholarly journals Unifying Thread-Level Speculation and Transactional Memory

Author(s):  
João Barreto ◽  
Aleksandar Dragojevic ◽  
Paulo Ferreira ◽  
Ricardo Filipe ◽  
Rachid Guerraoui
2012 ◽  
Vol 182-183 ◽  
pp. 639-643 ◽  
Author(s):  
Xiang Li ◽  
Fei Li ◽  
Chang Hao Wang

In this paper, five kinds of typical multi-core processers are compared from thread, cache, inter-core interconnect and etc. Two kinds of multi-core programming environments and some new programming languages are introduced. Thread-level speculation (TLS) and transactional memory (TM) are introduced to solve the problem of parallelization of sequential program. TLS automatically analyze and speculate the part of sequential process which can be parallel implement, and then automatically generate parallel code. TM systems provide an efficient and easy mechanism for parallel programming on multi-core processors. Typical TM likes TCC, UTM, LogTM, LogTM-SE and SigTM are introduced. Combined the TLS and TM can more effectively improve the sequential program running on the multi-core processors. Typical extended TM systems to support TLS likes TCC, TTM, PTT and STMlite are introduced.


2018 ◽  
Vol 51 (12) ◽  
pp. 105-113
Author(s):  
Matthew Le ◽  
Ryan Yates ◽  
Matthew Fluet

Author(s):  
Marina Shimchenko ◽  
Rubén Titos-Gil ◽  
Ricardo Fernández-Pascual ◽  
Manuel E. Acacio ◽  
Stefanos Kaxiras ◽  
...  

2006 ◽  
Vol 40 (5) ◽  
pp. 359-370 ◽  
Author(s):  
Michelle J. Moravan ◽  
Jayaram Bobba ◽  
Kevin E. Moore ◽  
Luke Yen ◽  
Mark D. Hill ◽  
...  
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