Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24× area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems

Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of current mobile applications. Recently emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of distinct memory classes render a new challenge for memory system design. Ideally, pages should be placed or migrated between the two types of memories according to the data objects’ access properties. Prior system software approaches exploit the program information from OS but at the cost of high software latency incurred by related kernel processes. Hardware approaches can avoid these latencies, however, hardware’s vision is constrained to a short time window of recent memory requests, due to the limited on-chip resources. In this work, we propose OpenMem: a hardware-software cooperative approach that combines the execution time advantages of pure hardware approaches with the data object properties in a global scope. First, we built a hardware-based memory manager unit (HMMU) that can learn the short-term access patterns by online profiling, and execute data migration efficiently. Then, we built a heap memory manager for the heterogeneous memory systems that allows the programmer to directly customize each data object’s allocation to a favorable memory device within the presumed object life cycle. With the programmer’s hints guiding the data placement at allocation time, data objects with similar properties will be congregated to reduce unnecessary page migrations. We implemented the whole system on the FPGA board with embedded ARM processors. In testing under a set of benchmark applications from SPEC 2017 and PARSEC, experimental results show that OpenMem reduces 44.6% energy consumption with only a 16% performance degradation compared to the all-DRAM memory system. The amount of writes to the NVM is reduced by 14% versus the HMMU-only, extending the NVM device lifetime.

Recruitment of a long-term memory supporting neural network during repeated maintenance of a multi-item abstract visual image in working memory

Humans can flexibly transfer information between different memory systems. Information in visual working memory (VWM) can for instance be stored in long-term memory (LTM). Conversely, information can be retrieved from LTM and temporarily held in WM when needed. It has previously been suggested that a neural transition from parietal- to midfrontal activity during repeated visual search reflects transfer of information from WM to LTM. Whether this neural transition indeed reflects consolidation and is also observed when memorizing a rich visual scene (rather than responding to a single target), is not known. To investigate this, we employed an EEG paradigm, in which abstract six-item colour-arrays were repeatedly memorized and explicitly visualized, or merely attended to. Importantly, we tested the functional significance of a potential neural shift for longer-term consolidation in a subsequent recognition task. Our results show a gradually enhanced- and sustained modulation of the midfrontal P170 component and a decline in parietal CDA, during repeated WM maintenance. Improved recollection/visualization of memoranda upon WM-cueing, was associated with contralateral parietal- and right temporal activity. Importantly, only colour-arrays previously held in WM, induced a greater midfrontal P170-response, together with left temporal- and late centro-parietal activity, upon re-exposure. These findings provide evidence for recruitment of an LTM-supporting neural network which facilitates visual WM maintenance.

Internet Use, Users, and Cognition: Determination of the Cognitive Relationships Between Internet-Based Technology and Internet Users

This study aims to investigate growing Internet use in relation to cognition. Existing literature suggests human capability to utilize the Internet as an external (transactive) memory source. Formational mechanisms of such transactive memory systems and comparative effects of Internet use on transactive memory and semantic memory are both relatively unknown points of research explored in this study.This study comprises two experimental memory task surveys, confirming and yielding findings in memory research. Semantic memory is negatively affected by notions of information saved online. An adaptive dynamic is also revealed—1) as users often have a vague idea of desired information before searching for it on the Internet, first accessing semantic memory serves as an aid for subsequent transactive memory use and 2) successful initial transactive memory access eliminates the need for subsequently accessing semantic memory for desired information. Internet users form and reinforce transactive memory systems with the Internet by repeatedly defaulting to first accessing semantic memory then transactive memory or to accessing transactive memory only, and decrease reliance on transactive memory systems by repeatedly defaulting to only semantic memory. Users have some degree of control over transactive memory systems they engage in, a phenomenon to be potentially explored in future research directions.

LargeGraph

Many out-of-GPU-memory systems are recently designed to support iterative processing of large-scale graphs. However, these systems still suffer from long time to converge because of inefficient propagation of active vertices’ new states along graph paths. To efficiently support out-of-GPU-memory graph processing, this work designs a system LargeGraph . Different from existing out-of-GPU-memory systems, LargeGraph proposes a dependency-aware data-driven execution approach , which can significantly accelerate active vertices’ state propagations along graph paths with low data access cost and also high parallelism. Specifically, according to the dependencies between the vertices, it only loads and processes the graph data associated with dependency chains originated from active vertices for smaller access cost. Because most active vertices frequently use a small evolving set of paths for their new states’ propagation because of power-law property, this small set of paths are dynamically identified and maintained and efficiently handled on the GPU to accelerate most propagations for faster convergence, whereas the remaining graph data are handled over the CPU. For out-of-GPU-memory graph processing, LargeGraph outperforms four cutting-edge systems: Totem (5.19–11.62×), Graphie (3.02–9.41×), Garaph (2.75–8.36×), and Subway (2.45–4.15×).

INFORMATION REPRODUCTION SYSTEMS IN INFORMATION BUSINESS LOGISTICS

The article considers the fundamentals of the information reproduction systems formation in the optoelectronic element base for information logistics systems. The use of optoelectronic elements for information processing has been considered, namely discrete optoelectronic digital systems, analog systems, optical memory systems, optical systems of input-output of information in computers, systems based on fiber devices of neuristor type. It is emphasized that modern logistics is impossible without the active use of information technology. The functions of information support of managerial influences can be performed by information technologies used today in logistics. To perform the tasks of financial flow management, these technologies can be supplemented by modules of eye-processing of the information. Logic-clock quantron automatic devices based on optocouplers are suitable for creating parallel information operating environments, which is a universal means of converting and presenting information. This approach leads to the creation of matrix-type devices that are able not only to receive information but also to process it. One of the promising areas of use of optoelectronic matrix systems is the creation of flat operating screens for parallel reception and display of information. The paper presents the classification of operating screens according to such features as: the principle of displaying information, the type of input information, the type of output information, the method of image formation, the number of consumers of the information. The analysis of electric circuit diagram of modern LED matrix video screens, in particular of a typesetting-modular design has been presented. A comparison of the forms of organization of matrix video screens is made, and it is emphasized that the most economical in terms of the number of memory trigger elements per one LED of the display cell is a video information system based on the structure of the third group video screen. The structure of the video information system is optimized according to the criterion of optimality – the maximum image quality on the matrix screen and the minimum screen complexity, which is determined by the circuit features of the microelectronic circuits.

Revisiting the Role of the Medial Temporal Lobe in Motor Learning

Classic taxonomies of memory distinguish explicit and implicit memory systems, placing motor skills squarely in the latter branch. This assertion is in part a consequence of foundational discoveries showing significant motor learning in amnesics. Those findings suggest that declarative memory processes in the medial temporal lobe (MTL) do not contribute to motor learning. Here, we revisit this issue, testing an individual (L. S. J.) with severe MTL damage on four motor learning tasks and comparing her performance to age-matched controls. Consistent with previous findings in amnesics, we observed that L. S. J. could improve motor performance despite having significantly impaired declarative memory. However, she tended to perform poorly relative to age-matched controls, with deficits apparently related to flexible action selection. Further supporting an action selection deficit, L. S. J. fully failed to learn a task that required the acquisition of arbitrary action–outcome associations. We thus propose a modest revision to the classic taxonomic model: Although MTL-dependent memory processes are not necessary for some motor learning to occur, they play a significant role in the acquisition, implementation, and retrieval of action selection strategies. These findings have implications for our understanding of the neural correlates of motor learning, the psychological mechanisms of skill, and the theory of multiple memory systems.