Bat Algorithm Based Low Power Mapping Methods for 3D Network-on-Chips

2017 ◽  
pp. 277-295 ◽  
Author(s):  
Jiazheng Li ◽  
Guozhi Song ◽  
Yue Ma ◽  
Cheng Wang ◽  
Baohui Zhu ◽  
...  
Keyword(s):  
Low Power ◽  
Bat Algorithm ◽  
3D Network ◽  
Power Mapping

Low Power Mapping Based on Improved Simulated Annealing Genetic Algorithm for 3D NoC

2019 ◽  
Vol 31 (4) ◽  
pp. 681
Author(s):  
Hanna He ◽  
Fang Fang ◽  
Wei Wang ◽  
Tian Chen ◽  
Jinliang Guo ◽  
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Keyword(s):  
Genetic Algorithm ◽  
Simulated Annealing ◽  
Low Power ◽  
Simulated Annealing Genetic Algorithm ◽  
Power Mapping

scholarly journals Low Power Mapping Algorithm Considering Data Transfer Time for CGRA

2012 ◽  
Vol 19A (1) ◽  
pp. 17-22
Author(s):  
Yong-Joo Kim ◽  
Jong-Hee Youn ◽  
Doo-San Cho ◽  
Yun-Heung Paek
Keyword(s):  
Low Power ◽  
Data Transfer ◽  
Transfer Time ◽  
Mapping Algorithm ◽  
Power Mapping

Hybrid Quantum Genetic Algorithm Used for Low-power Mapping in Network-on-chip

2017 ◽  
Vol 11 (2) ◽  
pp. 194-201 ◽  
Author(s):  
Tianhua Liu ◽  
Shoulin Yin ◽  
Jie Liu ◽  
Lin Teng
Keyword(s):  
Genetic Algorithm ◽  
Low Power ◽  
Network On Chip ◽  
Quantum Genetic Algorithm ◽  
On Chip ◽  
Power Mapping

Ultra Low Power Bioelectronics

2009 ◽  
Author(s):  
Rahul Sarpeshkar
Keyword(s):  
Low Power ◽  
Ultra Low Power
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