CityLightSense: A Participatory Sensing-based System for Monitoring and Mapping of Illumination levels

Adequate nighttime lighting of city streets is necessary for safe vehicle and pedestrian movement, deterrent of crime, improvement of the citizens’ perceptions of safety, and so on. However, monitoring and mapping of illumination levels in city streets during the nighttime is a tedious activity that is usually based on manual inspection reports. The advancement in smartphone technology comes up with a better way to monitor city illumination using a rich set of smartphone-equipped inexpensive but powerful sensors (e.g., light sensor, GPS, etc). In this context, the main objective of this work is to use the power of smartphone sensors and IoT-cloud-based framework to collect, store, and analyze nighttime illumination data from citizens to generate high granular city illumination map. The development of high granular illumination map is an effective way of visualizing and assessing the illumination of city streets during nighttime. In this article, an illumination mapping algorithm called Street Illumination Mapping is proposed that works on participatory sensing-based illumination data collected using smartphones as IoT devices to generate city illumination map. The proposed method is evaluated on a real-world illumination dataset collected by participants in two different urban areas of city Kolkata. The results are also compared with the baseline mapping techniques, namely, Spatial k-Nearest Neighbors, Inverse Distance Weighting, Random Forest Regressor, Support Vector Regressor, and Artificial Neural Network.

STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs

Accelerating finite-state automata benefits several emerging application domains that are built on pattern matching. In-memory architectures, such as the Automata Processor (AP), are efficient to speed them up, at least for outperforming traditional von-Neumann architectures. In spite of the AP’s massive parallelism, current APs suffer from poor memory density, inefficient routing architectures, and limited capabilities. Although these limitations can be lessened by emerging memory technologies, its architecture is still the major source of huge communication demands and lack of scalability. To address these issues, we present STAP , a Scalable TCAM-based architecture for Automata Processing . STAP adopts a reconfigurable array of processing elements, which are based on memristive Ternary CAMs (TCAMs), to efficiently implement Non-deterministic finite automata (NFAs) through proper encoding and mapping methods. The CAD tool for STAP integrates the design flow of automata applications, a specific mapping algorithm, and place and route tools for connecting processing elements by RRAM-based programmable interconnects. Results showed 1.47× higher throughput when processing 16-bit input symbols, and improvements of 3.9× and 25× on state and routing densities over the state-of-the-art AP, while preserving 10 4 programming cycles.

Colour Recognition Algorithm Based on Colour Mapping Knowledge for Wooden Building Image

In the cross-media image reproduction technology, the accurate transfer and reproduction of colour between different media are an important issue in the reproduction process, and the colour mapping technology is the key technology to effectively maintain the image details and improve the level of colour reproduction. Wooden structure in the image colour and colour piece is different, the image of each colour of visual perception is not independent, and every colour in the image pixels is affected by the surrounding pixels, but in the process of image map, without thinking of the pixel space, adjacent pixels of mutual influence in particular, do not let a person particularly be satisfied with the resulting map figure. In the process of image processing by traditional colour mapping algorithm, the colour distortion caused by colour component is ignored and the block diagram of colour mapping system is constructed. With the continuous development of mapping recognition algorithms, the maximum and minimum brightness values in the image are mapped to the maximum and minimum brightness values of the display device by linear mapping algorithm according to the flow of the established recognition algorithm. By establishing the colour adjustment method of the colour mapping image, the processing effect of the mapping algorithm is analysed. The results show that the brightness deviation of the image is reduced and the colour resolution is improved by the colour brightness compensation.

Slam Algorithms for Different Map Representations

The paper discusses the generalized simultaneous localization and mapping problem statement from the standpoint of the Bayesian approach and its relationship with algorithms for different map representations. The two-dimensional example describes the linearized simultaneous localization and mapping algorithm for the mobile platform in two-dimensional space.

Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.