Model Checking for Computation Tree Logic with Past Based on DNA Computing

Author(s):  
Yingjie Han ◽  
Qinglei Zhou ◽  
Linfeng Jiao ◽  
Kai Nie ◽  
Chunyan Zhang ◽  
...  
2020 ◽  
Vol 15 (5) ◽  
pp. 620-629
Author(s):  
Ying-Jie Han ◽  
Jian-Wei Wang ◽  
Chun Huang ◽  
Qing-Lei Zhou

Computation tree logic model checking is a formal verification technology that can ensure the correctness of systems. The vast storage density of deoxyribonucleic acid (DNA) molecules and the massive parallelism of DNA computing offer new methods for computation tree logic model checking. In this study, we propose a computation tree logic model checking method based on DNA computing. First, a system to-be-checked and a computation tree logic formula are encoded by single-stranded DNA molecules. Second, these singlestranded DNA molecules are mixed to spontaneously hybridize and form partial or complete double-stranded molecules. Finally, a series of molecular manipulations are applied to detect the double-stranded molecules so that the result whether the system satisfies the computation tree logic formula is obtained. Biological simulations confirm the validity of the new method.


2012 ◽  
Vol 23 (7) ◽  
pp. 1656-1668 ◽  
Author(s):  
Cong-Hua ZHOU ◽  
Zhi-Feng LIU ◽  
Chang-Da WANG

10.29007/c8jt ◽  
2018 ◽  
Author(s):  
Franz Weitl ◽  
Shin Nakajima

A new algorithm for incrementally generating counterexamples for the temporal description logic ALCCTL is presented. ALCCTL is a decidable combination of the description logic ALC and computation tree logic CTL that is expressive for content- and structure-related properties of web documents being verified by model checking. In the case of a specification violation, existing model checkers provide a single counterexample which may be large and complex. We extend existing algorithms for generating counterexamples in two ways. First, a coarse counterexample is generated initially that can be refined subsequently to the desired level of detail in an incremental manner. Second, the user can choose where and in which way a counterexample is refined. This enables the interactive step-by-step analysis of error scenarios according to the user's interest.We demonstrate in a case study on a web-based training document that the proposed approach reveals more errors and explains the cause of errors more precisely than the counterexamples of existing model checkers. In addition, we demonstrate that the proposed algorithm is sufficiently fast to enable smooth interaction even in the case of large documents.


2018 ◽  
Vol 52 (4) ◽  
pp. 539-563 ◽  
Author(s):  
Norihiro Kamide

Purpose The purpose of this paper is to develop new simple logics and translations for hierarchical model checking. Hierarchical model checking is a model-checking paradigm that can appropriately verify systems with hierarchical information and structures. Design/methodology/approach In this study, logics and translations for hierarchical model checking are developed based on linear-time temporal logic (LTL), computation-tree logic (CTL) and full computation-tree logic (CTL*). A sequential linear-time temporal logic (sLTL), a sequential computation-tree logic (sCTL), and a sequential full computation-tree logic (sCTL*), which can suitably represent hierarchical information and structures, are developed by extending LTL, CTL and CTL*, respectively. Translations from sLTL, sCTL and sCTL* into LTL, CTL and CTL*, respectively, are defined, and theorems for embedding sLTL, sCTL and sCTL* into LTL, CTL and CTL*, respectively, are proved using these translations. Findings These embedding theorems allow us to reuse the standard LTL-, CTL-, and CTL*-based model-checking algorithms to verify hierarchical systems that are modeled and specified by sLTL, sCTL and sCTL*. Originality/value The new logics sLTL, sCTL and sCTL* and their translations are developed, and some illustrative examples of hierarchical model checking are presented based on these logics and translations.


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