Implementation of Asynchronous Cache Memory

Advances in Intelligent Information Hiding and Multimedia Signal Processing - Smart Innovation, Systems and Technologies ◽

10.1007/978-981-13-9714-1_45 ◽

2019 ◽

pp. 413-421

Author(s):

Jigjidsuren Battogtokh

Keyword(s):

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Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences

IEICE Transactions on Electronics ◽

10.1587/transele.e99.c.936 ◽

2016 ◽

Vol E99.C (8) ◽

pp. 936-946

Author(s):

Ryotaro KOBAYASHI ◽

Ikumi KANEKO ◽

Hajime SHIMADA

Keyword(s):

Utilization Efficiency ◽

Cache Memory ◽

Data Utilization

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Mobile Cache Memory Optimization using Noise Reduction

International Journal of Computer Sciences and Engineering ◽

10.26438/ijcse/v6i11.925931 ◽

2018 ◽

Vol 6 (11) ◽

pp. 925-931

Author(s):

P. Amudha Bhomini ◽

Jayasudha J.S

Keyword(s):

Noise Reduction ◽

Cache Memory ◽

Memory Optimization ◽

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Aspects of Cache Memory and Instruction Buffer Performance

10.21236/ada604007 ◽

1987 ◽

Author(s):

Mark D. Hill

Keyword(s):

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Design algorithms for asynchronous operations in cache memory

ACM SIGMETRICS Performance Evaluation Review ◽

10.1145/1041911.1041914 ◽

1989 ◽

Vol 16 (2-4) ◽

pp. 21-21

Author(s):

Anna Hać

Keyword(s):

Cache Memory ◽

Design Algorithms

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Code integrity verification using cache memory monitoring

Information Security Journal A Global Perspective ◽

10.1080/19393555.2021.1902592 ◽

2021 ◽

pp. 1-11

Author(s):

Rajesh Kumar Shrivastava ◽

Varun Natu ◽

Chittaranjan Hota

Keyword(s):

Cache Memory ◽

Integrity Verification ◽

Code Integrity ◽

Memory Monitoring

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Leakage energy reduction in cache memory by data compression

ACM SIGARCH Computer Architecture News ◽

10.1145/1360464.1360472 ◽

2007 ◽

Vol 35 (5) ◽

pp. 17-24 ◽

Author(s):

Kiyofumi Tanaka ◽

Takahiro Kawahara

Keyword(s):

Data Compression ◽

Energy Reduction ◽

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On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory

2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS) ◽

10.1109/lascas51355.2021.9459175 ◽

2021 ◽

Author(s):

Sheetal Barekar ◽

Madan Mali

Keyword(s):

Defect Detection ◽

Detection Technique ◽

Cache Memory ◽

Test Time ◽

Chip Area ◽

Open Defect ◽

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Design of an area and energy-efficient last-level cache memory using STT-MRAM

Journal of Magnetism and Magnetic Materials ◽

10.1016/j.jmmm.2021.167882 ◽

2021 ◽

pp. 167882

Author(s):

Rajesh Saha ◽

Yogendra Pratap Pundir ◽

Pankaj Kumar Pal

Keyword(s):

Energy Efficient ◽

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A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.803023 ◽

2002 ◽

Vol 37 (10) ◽

pp. 1307-1317 ◽

Author(s):

Perng-Fei Lin ◽

J.B. Kuo

Keyword(s):

Cache Memory ◽

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Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system

IEICE Electronics Express ◽

10.1587/elex.13.20160276 ◽

2016 ◽

Vol 13 (12) ◽

pp. 20160276-20160276

Author(s):

Hongyeol Lim ◽

Gi-Ho Park

Keyword(s):

Memory System ◽

Cache Memory ◽

Cooperative Cache ◽

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