On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory

2021 ◽  
Author(s):  
Sheetal Barekar ◽  
Madan Mali
Keyword(s):  
Defect Detection ◽  
Detection Technique ◽  
Cache Memory ◽  
Test Time ◽  
Chip Area ◽  
Open Defect ◽  
On Chip

scholarly journals An Efficient Cache Organization for On-Chip Multiprocessor Networks

2015 ◽  
Vol 5 (3) ◽  
pp. 503
Author(s):  
Medhat Awadalla ◽  
Ahmed M. Sadek
Keyword(s):  
High Performance ◽  
Cache Coherence ◽  
Low Cost ◽  
System On Chip ◽  
Cache Memory ◽  
Processing Unit ◽  
Single Chip ◽  
Chip Area ◽  
Shared Cache ◽  
On Chip

To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes another challenging issue. In most System-on-Chip applications, a shared bus interconnection which needs an arbitration logic to serialize several bus access requests, is adopted to communicate with each integrated processing unit because of its low-cost and simple control characteristics. This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. It shows that having shared cache memory contributes to the performance improvement, however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. New interconnection mechanisms are needed to address these issues. This paper proposes an architectural paradigm in an attempt to gain the advantages of having shared cache with the avoidance of penalty imposed by the crossbar interconnect. The proposed architecture achieves smaller area occupation allowing more space to add additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper presents a modified cache coherence algorithm called Tuned-MESI. It is based on the typical MESI cache coherence algorithm however it is tuned and tailored for the suggested architecture. The achieved results of the conducted simulated experiments show that the developed architecture produces less broadcast operations compared to the typical algorithm.

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

2020 ◽  
pp. 1-13
Author(s):  
Gokul Chandrasekaran ◽  
P.R. Karthikeyan ◽  
Neelam Sanjeev Kumar ◽  
Vanchinathan Kumarasamy
Keyword(s):  
Ant Colony Optimization ◽  
Artificial Bee Colony ◽  
Optimization Algorithms ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Bee Colony ◽  
Ant Lion Optimization ◽  
Ant Lion ◽  
On Chip

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

Defect Detection Technique Based on Similarity Comparison of Token

2013 ◽  
Vol 13 (20) ◽  
pp. 4270-4277
Author(s):  
Guo Tao ◽  
Dong Guowei ◽  
Qin Hu ◽  
Long Baolian ◽  
Qu Tong ◽  
...  
Keyword(s):  
Defect Detection ◽  
Detection Technique ◽  
Similarity Comparison

scholarly journals Wood Defect Detection Based on Depth Extreme Learning Machine

2020 ◽  
Vol 10 (21) ◽  
pp. 7488
Author(s):  
Yutu Yang ◽  
Xiaolin Zhou ◽  
Ying Liu ◽  
Zhongkang Hu ◽  
Fenglong Ding
Keyword(s):  
Deep Learning ◽  
Extreme Learning Machine ◽  
Defect Detection ◽  
Clustering Algorithm ◽  
Classification Performance ◽  
Image Features ◽  
Test Time ◽  
Machine Model ◽  
Feature Extraction Method ◽  
Learning Machine

The deep learning feature extraction method and extreme learning machine (ELM) classification method are combined to establish a depth extreme learning machine model for wood image defect detection. The convolution neural network (CNN) algorithm alone tends to provide inaccurate defect locations, incomplete defect contour and boundary information, and inaccurate recognition of defect types. The nonsubsampled shearlet transform (NSST) is used here to preprocess the wood images, which reduces the complexity and computation of the image processing. CNN is then applied to manage the deep algorithm design of the wood images. The simple linear iterative clustering algorithm is used to improve the initial model; the obtained image features are used as ELM classification inputs. ELM has faster training speed and stronger generalization ability than other similar neural networks, but the random selection of input weights and thresholds degrades the classification accuracy. A genetic algorithm is used here to optimize the initial parameters of the ELM to stabilize the network classification performance. The depth extreme learning machine can extract high-level abstract information from the data, does not require iterative adjustment of the network weights, has high calculation efficiency, and allows CNN to effectively extract the wood defect contour. The distributed input data feature is automatically expressed in layer form by deep learning pre-training. The wood defect recognition accuracy reached 96.72% in a test time of only 187 ms.

RFIC Transformer With 12x Size Reduction and 15x Performance Enhancement by Self-Rolled-Up Membrane Nanotechnology

2015 ◽  
Author(s):  
Wen Huang ◽  
Moyang Li ◽  
Songbin Gong ◽  
Xiuling Li
Keyword(s):  
Millimeter Wave ◽  
Figure Of Merit ◽  
Performance Enhancement ◽  
Form Factors ◽  
Chip Area ◽  
Small Footprint ◽  
Working Frequency ◽  
Cmos Compatible ◽  
On Chip ◽  
Tubular Form

Two types of on-chip RFIC transformers based on CMOS compatible strain-induced self-rolled-up membrane (S-RuM) nanotechnology, with extremely small footprint, are demonstrated. The rolled-up transformers, with their 3D tubular form factors, dramatically reduce the substrate parasitic effects and push the maximum working frequency into millimeter wave bands with a coupling coefficient, k, as high as 0.92. The 3D stand-up nature also allows the tube transformers to be less susceptible to residue stress in the substrate and thus compatible with flexible platforms for wearable RF applications. The demonstrated samples with a turn ratio, n, of 5.5:1 only occupies 805 μm2 on-chip area (s) which is 12x smaller than that of the best planar transformer with the same turn ratio, and its figure of merit n·k/s, is therefore ∼ 6046/mm2, enhanced by 15x.

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