This article approaches the design of parallel routing Clos and Benes switching networks in Communication Technology. In communication, the transmission of data with less traffic and low latency are the biggest challenges. The conventional packet switching circuits takes the more power and high area to overcome this problem parallel routing algorithms are proposed. Clos and Benes networks are designed for the circuit switching systems where the switching configuration will be rearranged and it’s relatively low speed. Most of the existing parallel routing algorithms are not practical those are fail to interconnects the inputs with the matched outputs with less traffic. In this article, we designed Clos and Benes network. Clos and Benes networks are the Non-blocking switching Networks. Clos Switching network provides the better results like low area and less delay when compare with the Benes Switching Network. Clos and Benes non-blocking switching circuits are designed by Verilog HDL, Synthesized and simulated by XILINX 12.1 tool
Fault-Tolerant Circuit-Switching Networks
