CTRP3 as a novel biomarker in the plasma of Saudi children with autism

Background C1q/tumor necrosis factor-related protein-3 (CTRP3) has diverse functions: anti-inflammation, metabolic regulation, and protection against endothelial dysfunction. Methods The plasma level of CTRP3 in autistic patients (n = 32) was compared to that in controls (n = 37) using ELISA. Results CTRP3 was higher (24.7% with P < 0.05) in autistic patients than in controls. No association was observed between CTRP3 and the severity of the disorder using the Childhood Autism Rating Scale (CARS). A positive correlation between CARs and the age of patients was reported. Receiver operating characteristic (ROC) analysis demonstrated a low area under the curve (AUC) for all patients (0.636). Low AUCs were also found in the case of severe patients (0.659) compared to controls, but both values were statistically significant (P ≤ 0.05). Despite the small sample size, we are the first to find an association between CTRP3 and autism spectrum disorder (ASD).

Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.

This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40 to 100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of -132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6µ complementary metal oxide-semiconductor process.

Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications

In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.

Approximate Square Root Circuits with Low Latency and Power Dissipation

This paper proposes a series of approximate square root circuit designs with high accuracy, low latency, low area, and low power dissipation requirements. The proposed designs are constructed using an array of controlled add–subtract cell elements with both exact and approximate versions. The utility of the proposed designs are evaluated by utilizing them in an example image contrast enhancement application with demonstrably satisfactory results and large peak signal-to-noise ratios and structural similarity values. The accuracy and hardware characteristics of the proposed square root designs are also analyzed and compared with previously proposed state-of-the-art approximate square root designs. When applied to a 16-bit radicand (the number under the square root symbol), the proposed designs have the lowest error rates, normalized mean error distances, and mean relative error distances by at least 1.8x when compared to all previous methods using the same number of approximate cells. When the designs were synthesized using Synopsys Design Compiler with a 28 nm bulk CMOS process, the delay, area, power, and power-delay-product characteristics outperform all previous designs in all but a few cases. These results demonstrate that the proposed designs permit the use of a flexible range of approximate designs with varying accuracy and hardware overhead characteristics, and a suitable design can be selected based on the user design requirements.

Low-Power Low-Area architecture of Probability Density Function Estimation for Histogram Equalization

Estimation of Probability Density Functions (PDFs) in view of accessible information is critical issue emerging in various fields, for example, broadcast communications, machine learning, information mining, design pattern recognition and Personal Computer (PC) vision. In this paper, the Look-Up Table–Carry Select Adder-PDF (LUT-CSLA-PDF) mehod is implemented to increase system performance. The LUT is one of the fast way to recognize a complex function in the digital logic circuit. In this work, The FPGA (field programmable gate array) analysis, LUT, slices, flip flops, frequency are improved as well as ASIC (application specified integrated chip) implementation analysis an area, power, delay, Area Power Product (APP), Area Delay Product (ADP) are enhanced in LUT-CSLA-PDF technique compared to conventional methods.