Using Bounded Model Checking for Coverage Analysis of Safety-Critical Software in an Industrial Setting

2010 ◽  
Vol 45 (4) ◽  
pp. 397-414 ◽  
Author(s):  
Damiano Angeletti ◽  
Enrico Giunchiglia ◽  
Massimo Narizzano ◽  
Alessandra Puddu ◽  
Salvatore Sabina
Author(s):  
Fady Copty ◽  
Limor Fix ◽  
Ranan Fraer ◽  
Enrico Giunchiglia ◽  
Gila Kamhi ◽  
...  

Author(s):  
Daniel Große ◽  
Görschwin Fey ◽  
Rolf Drechsler

In this chapter the authors briefly review techniques used in formal hardware verification. An advanced flow emerges from integrating two major methodological improvements: debugging support and coverage analysis. The verification engineer can locate the source of a failure with an automatic debugging support. Components are identified which explain the discrepancy between the property and the circuit behavior. This method is complemented by an approach to analyze functional coverage of the proven Bounded Model Checking (BMC) properties. The approach automatically determines whether the property set is complete or not. In the latter case coverage gaps are returned. Both techniques are integrated in an enhanced verification flow. A running example demonstrates the resulting advantages.


2012 ◽  
Vol 23 (7) ◽  
pp. 1656-1668 ◽  
Author(s):  
Cong-Hua ZHOU ◽  
Zhi-Feng LIU ◽  
Chang-Da WANG

2013 ◽  
Vol 33 (3) ◽  
pp. 9-10
Author(s):  
Sagar Chaki

Author(s):  
Daniel Grosse ◽  
Robert Wille ◽  
Ulrich Kuehne ◽  
Rolf Drechsler

Author(s):  
Adrian Beer ◽  
Stephan Heidinger ◽  
Uwe Kühne ◽  
Florian Leitner-Fischer ◽  
Stefan Leue

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