A solution for automatic parallelization of sequential assembly code

Since modern multicore processors can execute existing sequential programs only on a single core, there is a strong need for automatic parallelization of program code. Relying on existing algorithms, this paper describes one new software solution tool for parallelization of sequential assembly code. The main goal of this paper is to develop the parallelizator which reads sequential assembler code and at the output provides parallelized code for MIPS processor with multiple cores. The idea is the following: the parser translates assembler input file to program objects suitable for further processing. After that the static single assignment is done. Based on the data flow graph, the parallelization algorithm separates instructions on different cores. Once sequential code is parallelized by the parallelization algorithm, registers are allocated with the algorithm for linear allocation, and the result at the end of the program is distributed assembler code on each of the cores. In the paper we evaluate the speedup of the matrix multiplication example, which was processed by the parallelizator of assembly code. The result is almost linear speedup of code execution, which increases with the number of cores. The speed up on the two cores is 1.99, while on 16 cores the speed up is 13.88.

Formal Modeling and Analysis of an Audio/Video Protocol: An Industrial Case Study Using UPPAAL

A formal and automatic verification of a real-life protocol is presented. The protocol, about 2800 lines of assembler code, has been used in products from the audio/video company Bang & Olufsen throughout more than a decade, and its purpose<br />is to control the transmission of messages between audio/video components over a single bus. Such communications may collide, and one essential purpose of the protocol is to detect such collisions. The functioning is highly dependent on<br />real-time considerations. Though the protocol was known to be faulty in that messages were lost occasionally, the protocol was too complicated in order for Bang & Olufsen to locate the bug using normal testing. However, using the real-time verification<br />tool UPPAAL, an error trace was automatically generated, which caused the detection of “the error” in the implementation. The error was corrected and the correction was automatically proven correct, again using UPPAAL. A future, and more automated, version of the protocol, where this error is fatal, will incorporate the correction. Hence, this work is an elegant demonstration of how model checking has had an impact on practical software development. The effort of modeling this protocol has in addition generated a number of suggestions for enriching the UPPAAL language. Hence, it’s also an excellent example of the reverse impact.

DESIGN AND IMPLEMENTATION OF A LOW-COST SYSTOLIC ARRAY SYSTEM

Actual implementations of systolic arrays are currently thought of as being large, complex and expensive. However, by taking advantage of commercially available multiplier/accumulator chips, a systolic array can be assembled as a low-cost, compact board-level system. We describe one such practical design which uses the NCR45CM16 CMOS multiplier/accumulator together with a specially-designed controller/router chip which handles the intracell and intercell communications functions. A demonstration four-cell linear systolic array has been constructed and tested using a PC/XT host computer. An assembler program, which also runs on the host, translates an assembler code representation of a systolic algorithm into object code. The object code is then transferred from the host to the systolic array for execution. Sample matrix computations demonstrate that the systolic array is functioning properly.