VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier

2020 ◽  
Vol 78 ◽  
pp. 103266
Author(s):  
Aditya Mandloi ◽  
Santosh Pawar
Keyword(s):  
Vlsi Design ◽  
Variable Block

VLSI design for diminished-1 multiplication of integers modulo a Fermat number

1988 ◽  
Vol 135 (3) ◽  
pp. 161 ◽  
Author(s):  
M. Benaissa ◽  
A. Pajayakrit ◽  
S.S. Dlay ◽  
A.G.J. Holt
Keyword(s):  
Vlsi Design ◽  
Fermat Number

Image Compression Using Vector Quantization with Variable Block Size Division

2010 ◽  
Vol 130 (8) ◽  
pp. 1431-1439 ◽  
Author(s):  
Hiroki Matsumoto ◽  
Fumito Kichikawa ◽  
Kazuya Sasazaki ◽  
Junji Maeda ◽  
Yukinori Suzuki
Keyword(s):  
Image Compression ◽  
Vector Quantization ◽  
Block Size ◽  
Variable Block

Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing

2010 ◽  
Vol E93-A (12) ◽  
pp. 2424-2432
Author(s):  
Kokoro KATO ◽  
Masakazu ENDO ◽  
Tadao INOUE ◽  
Shigetoshi NAKATAKE ◽  
Masaki YAMABE ◽  
...  
Keyword(s):  
Vlsi Design ◽  
Design Intent
Sign in / Sign up

Export Citation Format

Share Document