An optically-enabled chip–multiprocessor architecture using a single-level shared optical cache memory

Optical Switching and Networking ◽

10.1016/j.osn.2016.05.001 ◽

2016 ◽

Vol 22 ◽

pp. 54-68 ◽

Author(s):

P. Maniotis ◽

S. Gitzenis ◽

L. Tassiulas ◽

N. Pleros

Keyword(s):

Chip Multiprocessor ◽

Cache Memory ◽

Single Level ◽

Multiprocessor Architecture

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A novel Chip-Multiprocessor Architecture with optically interconnected shared L1 Optical Cache Memory

Optical Fiber Communication Conference ◽

10.1364/ofc.2014.th2a.9 ◽

2014 ◽

Author(s):

P. Maniotis ◽

S. Gitzenis ◽

L. Tassiulas ◽

N. Pleros

Keyword(s):

Chip Multiprocessor ◽

Cache Memory ◽

Multiprocessor Architecture

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High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing ◽

10.1109/siphotonics.2015.10 ◽

2015 ◽

Author(s):

Pavlos Maniotis ◽

Savvas Gitzenis ◽

Leandros Tassiulas ◽

Nikos Pleros

Keyword(s):

Chip Multiprocessor ◽

Cache Memory ◽

Single Level ◽

Shared Cache ◽

Multiprocessor Architectures

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On cache memory hierarchy for Chip-Multiprocessor

ACM SIGARCH Computer Architecture News ◽

10.1145/773365.773370 ◽

2003 ◽

Vol 31 (1) ◽

pp. 39-48 ◽

Author(s):

Mohamed M. Zahran

Keyword(s):

Memory Hierarchy ◽

Chip Multiprocessor ◽

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Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture

Languages and Compilers for Parallel Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-540-85261-2_18 ◽

2008 ◽

pp. 261-275

Author(s):

Slo-Li Chu

Keyword(s):

Block Scheduling ◽

Chip Multiprocessor ◽

Multiprocessor Architecture

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P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

Wireless Personal Communications ◽

10.1007/s11277-020-07529-2 ◽

2020 ◽

Vol 114 (4) ◽

pp. 3295-3319

Author(s):

Khyamling Parane ◽

B. M. Prabhu Prasad ◽

Basavaraj Talawar

Keyword(s):

Performance Evaluation ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Chip Multiprocessor ◽

Multiprocessor Architecture

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A novel 3D crossbar-based chip multiprocessor architecture

2013 Second International Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC) ◽

10.1109/jec-ecc.2013.6766390 ◽

2013 ◽

Author(s):

Mostafa Mahmoud ◽

Amr Wassal

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture

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An on-chip multiprocessor architecture with a non-blocking synchronization mechanism

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium ◽

10.1109/eurmic.1999.794505 ◽

1999 ◽

Author(s):

R. Kobayashi ◽

M. Iwata ◽

Y. Ogawa ◽

H. Ando ◽

T. Shimada

Keyword(s):

Chip Multiprocessor ◽

Synchronization Mechanism ◽

Multiprocessor Architecture ◽

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A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity

2007 IEEE International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2007.370528 ◽

2007 ◽

Author(s):

Engin Ipek ◽

Meyrem Kirman ◽

Nevin Kirman ◽

Jose F. Martinez

Keyword(s):

Chip Multiprocessor ◽

Software Diversity ◽

Multiprocessor Architecture

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Fair cache sharing and partitioning in a chip multiprocessor architecture

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004. ◽

10.1109/pact.2004.1342546 ◽

2004 ◽

Author(s):

Seongbeom Kim ◽

D. Chandra ◽

Yan Solihin

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture

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A complete strategy for testing an on-chip multiprocessor architecture

IEEE Design & Test of Computers ◽

10.1109/54.980050 ◽

2002 ◽

Vol 19 (1) ◽

pp. 18-28 ◽

Author(s):

C. Aktouf

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture ◽

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