Compiling image processing applications to reconfigurable hardware

2002 ◽  
Author(s):  
R. Rinker ◽  
J. Hammes ◽  
W.A. Najjar ◽  
W. Bohm ◽  
B. Draper
Keyword(s):  
Image Processing ◽  
Reconfigurable Hardware

Recent advances in computer vision and image processing using reconfigurable hardware

2005 ◽  
Vol 29 (8-9) ◽  
pp. 359-362 ◽  
Author(s):  
Miguel A. Vega-Rodríguez ◽  
Juan M. Sánchez-Pérez ◽  
Juan A. Gómez-Pulido
Keyword(s):  
Image Processing ◽  
Computer Vision ◽  
Reconfigurable Hardware ◽  
Recent Advances

scholarly journals Multiloop Parallelisation Using Unrolling and Fission

2010 ◽  
Vol 2010 ◽  
pp. 1-10 ◽  
Author(s):  
Yuet Ming Lam ◽  
José Gabriel F. Coutinho ◽  
Chun Hok Ho ◽  
Philip Heng Wai Leong ◽  
Wayne Luk
Keyword(s):  
Image Processing ◽  
Speech Recognition ◽  
Body Problem ◽  
Heterogeneous Computing ◽  
Computing System ◽  
Reconfigurable Hardware ◽  
N Body Problem ◽  
Size Constraints ◽  
Multiple Tasks ◽  
Heterogeneous Computing System

A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling.

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