Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems
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2003 ◽
Vol 52
(10)
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pp. 1332-1346
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1995 ◽
Vol 44
(2)
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pp. 292-301
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2016 ◽
Vol 45
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pp. 164-175
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