Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems

Author(s):  
Antonio Marti-Campoy ◽  
Francisco Rodriguez-Ballester
1995 ◽  
Vol 44 (2) ◽  
pp. 292-301 ◽  
Author(s):  
Fuxing Wang ◽  
K. Ramamritham ◽  
J.A. Stankovic

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