From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

Author(s):  
Joao Andrade ◽  
Nithin George ◽  
Kimon Karras ◽  
David Novo ◽  
Vitor Silva ◽  
...  
Author(s):  
Imed Saad Ben Dhaou ◽  
Hannu Tenhunen

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.


Author(s):  
J. L. Van Meerbergen ◽  
P. E. R. Lippens ◽  
W. F. J. Verhaegh ◽  
A. Van Der Werf

Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI

2019 ◽  
Vol 12 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Julian Oppermann ◽  
Melanie Reuter-Oppermann ◽  
Lukas Sommer ◽  
Andreas Koch ◽  
Oliver Sinnen

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