Latency Insensitive Design Styles for FPGAs

2018 28th International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2018.00068 ◽

2018 ◽

Author(s):

Mustafa Abbas ◽

Vaughn Betz

Keyword(s):

Latency Insensitive

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Fractional register calculation and optimization in scheduling based Latency-Insensitive design

Engineering Science and Technology an International Journal ◽

10.1016/j.jestch.2019.04.013 ◽

2020 ◽

Vol 23 (1) ◽

pp. 204-210

Author(s):

Mahdi Zare

Keyword(s):

Latency Insensitive

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Performance analysis and optimization of latency insensitive systems

Proceedings 37th Design Automation Conference ◽

10.1145/337292.337441 ◽

2000 ◽

Author(s):

Luca P. Carloni ◽

Alberto L. Sangiovanni-Vincentelli

Keyword(s):

Performance Analysis ◽

Latency Insensitive

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Quantifying the cost and benefit of latency insensitive communication on FPGAs

Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays - FPGA '14 ◽

10.1145/2554688.2554786 ◽

2014 ◽

Author(s):

Kevin E. Murray ◽

Vaughn Betz

Keyword(s):

Cost And Benefit ◽

The Cost ◽

Latency Insensitive

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Throughput optimization for latency-insensitive system with minimal queue insertion

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) ◽

10.1109/aspdac.2011.5722257 ◽

2011 ◽

Author(s):

Juinn-Dar Huang ◽

Yi-Hang Chen ◽

Ya-Chien Ho

Keyword(s):

Throughput Optimization ◽

Latency Insensitive

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Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240952 ◽

2004 ◽

Author(s):

M. Dall'Osso ◽

G. Biccari ◽

L. Giovannini ◽

D. Bertozzi ◽

L. Benini

Keyword(s):

Network On Chip ◽

On Chip ◽

Latency Insensitive

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Topology-based optimization of maximal sustainable throughput in a latency-insensitive system

2007 44th ACM/IEEE Design Automation Conference ◽

10.1145/1278480.1278586 ◽

2007 ◽

Author(s):

Rebecca L. Collins ◽

Luca P. Carloni

Keyword(s):

Latency Insensitive

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Throughput enhancement for repetitive internal cores in latency-insensitive systems

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2011.0064 ◽

2012 ◽

Vol 6 (5) ◽

pp. 342-352 ◽

Author(s):

M. Zare ◽

S. Hessabi ◽

M. Goudarzi

Keyword(s):

Throughput Enhancement ◽

Latency Insensitive

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Performance analysis of latency-insensitive systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.854636 ◽

2006 ◽

Vol 25 (3) ◽

pp. 469-483 ◽

Author(s):

Ruibing Lu ◽

Cheng-Kok Koh

Keyword(s):

Performance Analysis ◽

Latency Insensitive

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Another Glance at Relay Stations in Latency-Insensitive Design

Electronic Notes in Theoretical Computer Science ◽

10.1016/j.entcs.2005.05.035 ◽

2006 ◽

Vol 146 (2) ◽

pp. 41-59 ◽

Author(s):

Julien Boucaron ◽

Jean-Vivien Millo ◽

Robert De Simone

Keyword(s):

Latency Insensitive ◽

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Recovery-based resilient latency-insensitive systems

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 ◽

10.7873/date.2014.116 ◽

2014 ◽

Author(s):

Yuankai Chen ◽

Xuan Zeng ◽

Hai Zhou

Keyword(s):

Latency Insensitive

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