Proceedings 21st International Conference on Computer Design

Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240952 ◽

2004 ◽

Cited By ~ 54

Author(s):

M. Dall'Osso ◽

G. Biccari ◽

L. Giovannini ◽

D. Bertozzi ◽

L. Benini

Keyword(s):

Network On Chip ◽

On Chip ◽

Latency Insensitive

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Simplifying SoC design with the customizable control processor platform

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240928 ◽

2004 ◽

Author(s):

C.R. Ogilvie ◽

R. Ray ◽

R. Devins ◽

M. Kautzman ◽

M. Hale ◽

...

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Verification of timed circuits with failure directed abstractions

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240869 ◽

2004 ◽

Cited By ~ 5

Author(s):

H. Zheng ◽

C.J. Myers ◽

D. Walter ◽

S. Little ◽

T. Yoneda

Keyword(s):

Timed Circuits

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Knapbind: an area-efficient binding algorithm for low-leakage datapaths

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240935 ◽

2004 ◽

Cited By ~ 13

Author(s):

Chandramouli Gopalakrishnan ◽

Srinivas Katkoori

Keyword(s):

Low Leakage ◽

Area Efficient

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On combining pinpoint test set relaxation and run-length codes for reducing test data volume

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240925 ◽

2004 ◽

Cited By ~ 3

Author(s):

S. Kajihara ◽

Y. Doi ◽

Lei Li ◽

Krishnendu Chakrabarty

Keyword(s):

Test Data ◽

Test Set ◽

Run Length ◽

Data Volume

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Low-density parity-check decoder architecture for high throughput optical fiber channels

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240949 ◽

2004 ◽

Cited By ~ 3

Author(s):

Anand Selvarathinam ◽

E. Kim ◽

G. Choi

Keyword(s):

Optical Fiber ◽

High Throughput ◽

Low Density ◽

Parity Check ◽

Low Density Parity Check ◽

Decoder Architecture ◽

Fiber Channels

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An energy-aware simulation model and transaction protocol for dynamic workload distribution in mobile ad hoc networks

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240939 ◽

2004 ◽

Author(s):

F. Ghasemi-Tari ◽

P. Rong ◽

M. Pedram

Keyword(s):

Ad Hoc Networks ◽

Simulation Model ◽

Mobile Ad Hoc Networks ◽

Ad Hoc ◽

Energy Aware ◽

Workload Distribution ◽

Mobile Ad Hoc ◽

Hoc Networks

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Non-crossing OBDDs for mapping to regular circuit structures

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240916 ◽

2004 ◽

Cited By ~ 5

Author(s):

A. Cao ◽

C.-K. Koh

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Power fluctuation minimization during behavioral synthesis using ILP-based datapath scheduling

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240937 ◽

2004 ◽

Cited By ~ 1

Author(s):

S.P. Mohanty ◽

N. Ranganathan ◽

S.K. Chappidi

Keyword(s):

Power Fluctuation ◽

Behavioral Synthesis

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On reducing register pressure and energy in multiple-banked register files

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240867 ◽

2004 ◽

Cited By ~ 8

Author(s):

J. Abella ◽

A. Gonzalez

Keyword(s):

Register Files ◽

Register Pressure

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Proceedings 21st International Conference on Computer Design
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

Simplifying SoC design with the customizable control processor platform

Verification of timed circuits with failure directed abstractions

Knapbind: an area-efficient binding algorithm for low-leakage datapaths

On combining pinpoint test set relaxation and run-length codes for reducing test data volume

Low-density parity-check decoder architecture for high throughput optical fiber channels

An energy-aware simulation model and transaction protocol for dynamic workload distribution in mobile ad hoc networks

Non-crossing OBDDs for mapping to regular circuit structures

Power fluctuation minimization during behavioral synthesis using ILP-based datapath scheduling

On reducing register pressure and energy in multiple-banked register files

Export Citation Format

Proceedings 21st International Conference on Computer DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

Simplifying SoC design with the customizable control processor platform

Verification of timed circuits with failure directed abstractions

Knapbind: an area-efficient binding algorithm for low-leakage datapaths

On combining pinpoint test set relaxation and run-length codes for reducing test data volume

Low-density parity-check decoder architecture for high throughput optical fiber channels

An energy-aware simulation model and transaction protocol for dynamic workload distribution in mobile ad hoc networks

Non-crossing OBDDs for mapping to regular circuit structures

Power fluctuation minimization during behavioral synthesis using ILP-based datapath scheduling

On reducing register pressure and energy in multiple-banked register files

Proceedings 21st International Conference on Computer Design
Latest Publications