Design and Analysis of a Novel 8X8 Bit Signed/Unsigned Synchronous MAC Architecture Using Clock Gating Scheme for Fixed-Point Arithmetic

Author(s):  
Rajkumar Sarma ◽  
Sandeep Dhariwal ◽  
Shruti Jain
1990 ◽  
Vol 2 (3) ◽  
pp. 363-373 ◽  
Author(s):  
Paul W. Hollis ◽  
John S. Harper ◽  
John J. Paulos

This paper presents a study of precision constraints imposed by a hybrid chip architecture with analog neurons and digital backpropagation calculations. Conversions between the analog and digital domains and weight storage restrictions impose precision limits on both analog and digital calculations. It is shown through simulations that a learning system of this nature can be implemented in spite of limited resolution in the analog circuits and using fixed point arithmetic to implement the backpropagation algorithm.


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