A partitioning algorithm for parallel discrete event gate-level logic simulations is
proposed in this paper. Unlike most other partitioning algorithms, the proposed
algorithm preserves computation concurrency by assigning to processors circuit gates
that can be evaluated at about the same time. As a result, the improved concurrency
preserving partitioning (iCPP) algorithm can provide better load balancing throughout
the period of a parallel simulation. This is especially important when the algorithm is
used together with a Time Warp simulation where a high degree of concurrency can lead
to fewer rollbacks and better performance. The algorithm consists of three phases and
three conflicting goals can be separately considered so to reduce computational
complexity.To evaluate the quality of partitioning algorithms in terms of preserving concurrency,
a concurrency metric that requires neither sequential nor parallel simulation is
proposed. A levelization technique is used in computing the metric so to determine
gates which can be evaluated at about the same time. A parallel gate-level logic
simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the
performance of the iCPP algorithm. The results are compared with several other
partitioning algorithms to show that the iCPP algorithm does preserve concurrency
pretty well and reasonable speedup may be achieved with the algorithm.