A line labeling and region growing based algorithm for binary image connected component labeling

Author(s):  
Feng Zhang ◽  
Shunyong Zhou ◽  
Wenling Xie
Author(s):  
LIFENG HE ◽  
YUYAN CHAO ◽  
KENJI SUZUKI

This paper presents a run- and label-equivalence-based one-and-a-half-scan algorithm for labeling connected components in a binary image. Major differences between our algorithm and conventional label-equivalence-based algorithms are: (1) all conventional label-equivalence-based algorithms scan all pixels in the given image at least twice, whereas our algorithm scans background pixels once and object pixels twice; (2) all conventional label-equivalence-based algorithms assign a provisional label to each object pixel in the first scan and relabel the pixel in the later scan(s), whereas our algorithm assigns a provisional label to each run in the first scan, and after resolving label equivalences between runs, by using the recorded run data, it assigns each object pixel a final label directly. That is, in our algorithm, relabeling of object pixels is not necessary any more. Experimental results demonstrated that our algorithm is highly efficient on images with many long runs and/or a small number of object pixels. Moreover, our algorithm is directly applicable to run-length-encoded images, and we can obtain contours of connected components efficiently.


2010 ◽  
Vol 21 (03) ◽  
pp. 405-425 ◽  
Author(s):  
YASUAKI ITO ◽  
KOJI NAKANO

Connected component labeling is a process that assigns unique labels to the connected components of a binary image. The main contribution of this paper is to present a low-latency hardware connected component labeling algorithm for k-concave binary images designed and implemented in FPGA. Pixels of a binary image are given to the FPGA in raster order, and the resulting labels are also output in the same order. The advantage of our labeling algorithm is low latency and to use a small internal storage of the FPGA. We have implemented our hardware labeling algorithm in an Altera Stratix Family FPGA, and evaluated the performance. The implementation result shows that for a 10-concave binary image of 2048 × 2048, our connected component labeling algorithm runs in approximately 70ms and its latency is approximately 750µs.


2009 ◽  
Vol 42 (9) ◽  
pp. 1977-1987 ◽  
Author(s):  
Lifeng He ◽  
Yuyan Chao ◽  
Kenji Suzuki ◽  
Kesheng Wu

2020 ◽  
Vol 8 (2) ◽  
pp. 119
Author(s):  
Cokorda Gde Teresna Jaya ◽  
I Gede Arta Wibawa

Certificate is one of the documents that can be used as evidence of ownership or an event. For example, when certificate used as requirement to participate in an event. If a document is made as a requirement, of course the file verification process will be done. Seeing the time optimization problem when verifying the file, the authors carry out research by segmenting important data contained in a certificate as an initial step in the development of an automatic document verification system. The segmentation process carried out in this study uses the Connected Component Labeling method in determining the area to be segmented and Automatic Cropping to cut the results of the segmentation process. By using these two methods obtained an accuracy of 60% with a total of 15 pieces of test data


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