Parallel Algorithm of Hierarchical Phrase Machine Translation Based on Distributed Network Memory

Machine translation has developed rapidly. But there are some problems in machine translation, such as good reading, unable to reflect the mood and context, and even some language machines can not recognize. In order to improve the quality of translation, this paper uses the SSCI method to improve the quality of translation. It is found that the translation quality of hierarchical phrases is significantly improved after using the parallel algorithm of machine translation, which is about 9% higher than before, and the problem of context free grammar is also solved. The research also found that the use of parallel algorithm can effectively reduce the network memory occupation, the original 10 character content, after using the parallel algorithm, only need to occupy 8 characters, the optimization reaches 20%. This means that the parallel algorithm of hierarchical phrase machine translation based on distributed network memory can play a very important role in machine translation.

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

A Novel Parallel Algorithm with Map Segmentation for Multiple Geographical Feature Label Placement Problem

Multiple geographical feature label placement (MGFLP) is an NP-hard problem that can negatively influence label position accuracy and the computational time of the algorithm. The complexity of such a problem is compounded as the number of features for labeling increases, causing the execution time of the algorithms to grow exponentially. Additionally, in large-scale solutions, the algorithm possibly gets trapped in local minima, which imposes significant challenges in automatic label placement. To address the mentioned challenges, this paper proposes a novel parallel algorithm with the concept of map segmentation which decomposes the problem of multiple geographical feature label placement (MGFLP) to achieve a more intuitive solution. Parallel computing is then utilized to handle each decomposed problem simultaneously on a separate central processing unit (CPU) to speed up the process of label placement. The optimization component of the proposed algorithm is designed based on the hybrid of discrete differential evolution and genetic algorithms. Our results based on real-world datasets confirm the usability and scalability of the algorithm and illustrate its excellent performance. Moreover, the algorithm gained superlinear speedup compared to the previous studies that applied this hybrid algorithm.

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.