Analysis of common mode voltage-"neutral shift" in medium voltage PWM adjustable speed drive (MV-ASD) systems

Author(s):  
D. Rendusara ◽  
E. Cengelci ◽  
P. Enjeti ◽  
V.R. Stefanovic ◽  
W. Gray
2000 ◽  
Vol 15 (6) ◽  
pp. 1124-1133 ◽  
Author(s):  
D.A. Rendusara ◽  
E. Cengelci ◽  
P.N. Enjeti ◽  
V.R. Stefanovic ◽  
J.W. Gray

2015 ◽  
Vol 30 (5) ◽  
pp. 2828-2839 ◽  
Author(s):  
Pawan Garg ◽  
Somasundaram Essakiappan ◽  
Harish S. Krishnamoorthy ◽  
Prasad N. Enjeti

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1607
Author(s):  
Chang-Hwan Park ◽  
In-Kyo Seo ◽  
Belete Belayneh Negesse ◽  
Jong-su Yoon ◽  
Jang-Mok Kim

Low level modular multilevel converter (MMC) is a promising candidate for medium voltage applications such as MVDC (medium voltage DC current) transmission and megawatt machine drives. Unlike high-level MMC using nearest level modulation (NLM), the low-level MMC using the pulse width modulation (PWM) or NLM + PWM is affected by a common mode voltage (CMV) due to a frequent change of a switching state. This CMV causes electromagnetic interference (EMI) noise, common mode current (CMC) and bearing current leading to a reduction in the efficiency and durability of the motor drive system. Therefore, this paper provides a mathematical analysis on how the switching state affects the CMV and proposes three software based CMV reduction algorithms for the low level MMC system. To reflect the characteristic of MMC modulation strategy for upper and lower reference voltage independently, two separate space vectors are used. Based on the analysis, three different CMV reduction algorithms (complete CMV reduction (CCR), DPWM CMV reduction (DCR) and partial CMV reduction (PCR)) are proposed using NLC + PWM modulation strategy. The performance of the proposed CMV reduction algorithms was verified by both simulation and experimental result.


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