scholarly journals Analysis of Bounds on Hybrid Vector Clocks

2018 ◽  
Vol 29 (9) ◽  
pp. 1947-1960 ◽  
Author(s):  
Sorrachai Yingchareonthawornchai ◽  
Duong N. Nguyen ◽  
Sandeep S. Kulkarni ◽  
Murat Demirbas
Keyword(s):  
2020 ◽  
Vol 30 (3) ◽  
pp. 441-464
Author(s):  
Loïg Jezequel ◽  
Agnes Madalinski ◽  
Stefan Schwoon

2006 ◽  
Vol 66 (2) ◽  
pp. 221-237 ◽  
Author(s):  
Anish Arora ◽  
Sandeep S. Kulkarni ◽  
Murat Demirbas
Keyword(s):  

2001 ◽  
Vol 11 (01) ◽  
pp. 65-76
Author(s):  
LUCIANA ARANTES ◽  
DENIS POITRENAUD ◽  
PIERRE SENS ◽  
BERTIL FOLLIOT

In this article, we introduce a new logical clock, the barrier-lock clock, whose conception is based on the lazy release consistency memory model (LRC) supported by several distributed shared memory (DSM) systems. Since in the LRC, the propagation of shared memory updates performed by the processes of a parallel application is induced by lock and barrier operations, our logical clock has been modeled on those operations. Each barrier-lock times-tamp encodes the synchronization operation with which it is associated. Its size is not dependent on the number of processes of the system, as the traditional logical vector clocks, but it is proportional to the number of locks. The barrier-lock time characterizes the causality of shared memory updates performed by processes of a parallel application running on a LRC-based DSM system. A formal proof and experimental tests have confirmed such property.


1992 ◽  
Vol 43 (1) ◽  
pp. 47-52 ◽  
Author(s):  
Mukesh Singhal ◽  
Ajay Kshemkalyani

2014 ◽  
Author(s):  
Hyun-Ji Kim ◽  
Byoung-Kwi Lee ◽  
Ok-Kyoon Ha ◽  
Yong-Kee Jun

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